Rosemary Ainslie circuit demonstration on Saturday March 12th 2011

[poynt99]

Correct.

However, power mosfets, in general use with switched power circuits are usually biased at the gate with a nominal 10 volts or more.

Thanks for posting hoptoad.

In this circuit, the MOSFETs are being applied in more of a "linear" sense, and V_GS never (or rarely) approaches anything more that 5V, one polarity or the other.

.99

[neptune]

@poynt99 . Thankyou for answering my questions.

[Rosemary Ainslie]

Rose,

Unless the demonstration video footage is not authentic, I have already painstakingly well established what the actual "AS-BUILT" circuit connections are and posted them. Have you seen those posts?

It is quite clear from the video footage that the actual schematic is per the one below, with the exception for the function generator, shown here as a fixed DC source. In particular, the CSR is most definitely connected to the Q1 source and Q2 Gate as shown.

Poynty - it does not make a blind bit of difference to the waveform or the results whether the ground from the signal generator is directly on the shared negative rail or if it's in series with the shunt.  The fact that it was set up that way at the demo was happenstance. The fact is that it's more convenient to keep the ground on that shared rail because we were running two oscilloscopes and 4 channels - concurrently.  That made the junction at D rather crowded.  In point of fact it is normally at the pin marked at D on the video.  But that's because I usually only ever use the LeCroy.  I've just checked the video and the board.  Right now and for those shots I took to argue your 'undersampling' quibble - it is and usually is positioned at D - in series with the shunt.  I wonder what difference it would make to your waveforms if you placed it at the negative rail.  I'd be interested to see.  I suspect very little.  But in any event it's wrong.  It is properly in series with the CSR.

Why are you changing the pin designation on "Q2-5"? The "g" means "gate", and "s" means "source".

I know this Poynty.  That's exactly why I needed to transpose it.  Think it through.  We swap the Gate and the Source.  We do not change the drain.  Am I talking to myself here?  Let me try this again.  Q1 takes a positive current from the battery via a postive charge applied to the gate.  That's during the 'on' time.  Then.  Let's just take it that we've got a battery signal source because that gets to the meat of the issue best.  Q2 takes a positive charge from the signal supplying battery via a postive charge applied at the gate.  The same thing.  I'ts only NEGATIVE relative to Q1.  That transposition effectlvely generates a POSITIVE CHARGE at the gate.  Which is precisely what the MOSFET wants.  It's been built that way.  I do hope the penny drops.  Effectively the MOSFET is reading the source as the drain and the drain as the source relative, that is, to Q1.

Regarding that small capacitor in parallel with the load, it is of course not a discrete component of the load, but all inductors have some capacitance associated with them, and it was included only to allow for a more accurate simulation. The consequence however of removing it is minimal. It is of no concern in actuality.

Good.  Let's get rid of it. 

Kindest regards,
Rosemary

Added.
And some more.

[poynt99]

Now that the "as-built" circuit connections have been firmly re-established (reference diagram depicted in Simplification01_schema01.png), would anyone like to try and predict what changes might occur in the circuit operation if Q1 is completely removed from the circuit, and no capacitor or diode connected in its place?

.99

[Rosemary Ainslie]

Now that the "as-built" circuit connections have been firmly re-established (reference diagram depicted in Simplification01_schema01.png), would anyone like to try and predict what changes might occur in the circuit operation if Q1 is completely removed from the circuit, and no capacitor or diode connected in its place?

.99

Yes.  I would.  I already know.  PROVIDED you keep the bias of the diode at the drain as per Q2 as you've SHOWN it and not as our circuit actually has it - then it won't make a blind bit of difference.  The circuit will oscillate.  But to what end?

This is where I get more than a little exasperated Poynty.  Are we simply to attempt more and more schematics to generate an oscillation?  Is that all the merit you see here?  The POINT of the study of that oscillation was not HOW TO GENERATE IT - but to consider that it's there at all.  I am reasonably satisfied that it will persist certainly as long as a charge is applied at the Gate.  And when we do get that oscillation then we have current moving to and from the battery that has all kinds of conservation benefits.  But we also need to 'up the ante' and that means that all this discourse could have been spent in studying how to get the 'extreme' values in those oscillations.  For instance - at certain settings the voltage peak to peak across the CSR is 4 volts or thereby.  But at other settings - usually with adjustments to the offset and the duty cycle - it's possible to get voltages that are 10 times that value and oscillations that are greater by a factor of 3.  And so it goes. 

We need to move on.

Rosemary