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Overunity Machines Forum



Testing the TK Tar Baby

Started by TinselKoala, March 25, 2012, 05:11:53 PM

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TinselKoala

PW, thank you for that very clear and detailed description of the action of the NERD circuit and the role of the FG during both phases of operation, gate signal HI or signal LO. You have explained in detail a phenomenon that I have actually repeatedly commented on and which .99 has also noticed in his simulations.

Picowatt said,
Quote(one would have thought that this "clamping action" that is obvious in all 'scope captures when the FG is a negative voltage, regardless of the FG offset settings, would have caused "someone" to wonder why.  And clearly it is due to the Vdrop across Rgen when Q2 bias current is flowing thru the FG)

It's what I've been calling the "voltage floor" and I've illustrated it several times in my videos of Tar Baby and it's very clear in all of the Ainslie scope traces that use a negative (gate signal LO) gate drive portion. She has the FG's offset cranked all the way negative, according to her descriptions, and yet the voltage always bottoms out at -4 V plus noise. I have indeed wondered why, and I had come up with the same explanation you have done, but I could not express it so clearly and concisely. It surprised me when I first encountered it using my F43, which, if something were not "loading it up" (as I mentioned in some early videos) should have been able easily to reach -20V driving a mosfet gate.


However, it seems that your analysis is just more "pearls before swine", because this seems to be the typical Ainslie non-response which always has to include some kind of insult, lie, or threat.
Ainslie says:
QuoteI started reading your post and just got disheartened at its length and obscurity.  Forgive me - if you're depending on my reading it I, unfortunately, just don't have the appetite. I have a very short attention span and absolutely no interest in your opinions.  Unless it was not intended for my readership.  In which case all is dandy.
and
QuoteThis is balderdash.  From inception to conclusion. 

So much for attempts at technical explanations. She must not be able to see the shapes of your words, picowatt. Maybe you should use a larger font.


TinselKoala

Quote from: picowatt on June 29, 2012, 11:13:57 AM
And again, in this short post, you demonstrate your lack of understanding regarding the operation of a function generator and how you circuit operates.

It is truly pathetic, and indeed, you should be "embarrassed".

She apparently has no clue that voltages are relative. That's not part of her "model". The fact that the FG's black or "ground" wire can put out a Positive voltage at the very same time that the red or "probe" wire is putting out a Negative voltage must be an astonishing mystery to her, impossible to explain. Start talking about gradients in electric fields, or just why Sassy ClassE can light up neon bulbs wirelessly in a large volume of space, and watch her eyes roll back in her head as her brain's ego filters kick in and prevent any further input.

picowatt

Quote from: TinselKoala on June 29, 2012, 11:32:15 AM
PW, thank you for that very clear and detailed description of the action of the NERD circuit and the role of the FG during both phases of operation, gate signal HI or signal LO. You have explained in detail a phenomenon that I have actually repeatedly commented on and which .99 has also noticed in his simulations.

Picowatt said,
It's what I've been calling the "voltage floor" and I've illustrated it several times in my videos of Tar Baby and it's very clear in all of the Ainslie scope traces that use a negative (gate signal LO) gate drive portion. She has the FG's offset cranked all the way negative, according to her descriptions, and yet the voltage always bottoms out at -4 V plus noise. I have indeed wondered why, and I had come up with the same explanation you have done, but I could not express it so clearly and concisely. It surprised me when I first encountered it using my F43, which, if something were not "loading it up" (as I mentioned in some early videos) should have been able easily to reach -20V driving a mosfet gate.


However, it seems that your analysis is just more "pearls before swine", because this seems to be the typical Ainslie non-response which always has to include some kind of insult, lie, or threat.
Ainslie says:and
So much for attempts at technical explanations. She must not be able to see the shapes of your words, picowatt. Maybe you should use a larger font.

TK,

Yes, everything in my reply #3356 has been fully proven and verified via .99's sims and your empirical data.  Yet she prefers to remain ignorant of the facts.  It is truly amazing, but not unexpected.  Afterall, consider all the data and text that would need correction/retraction from her papers if she were to actually understand all that is discussed in that post.  It seems she would rather just bury her head in the sand and refuse to believe readily accepted electronic circuit operation and proven facts.  Even her own 'scope captures clearly confirm the operation of Q2 as discussed, but she refuses to see it.

She will never perform any due diligence that may confirm everything in my post, as she is too afraid to do so.

PW



   

picowatt

Quote from: TinselKoala on June 29, 2012, 11:54:35 AM
She apparently has no clue that voltages are relative. That's not part of her "model". The fact that the FG's black or "ground" wire can put out a Positive voltage at the very same time that the red or "probe" wire is putting out a Negative voltage must be an astonishing mystery to her, impossible to explain. Start talking about gradients in electric fields, or just why Sassy ClassE can light up neon bulbs wirelessly in a large volume of space, and watch her eyes roll back in her head as her brain's ego filters kick in and prevent any further input.

TK,

This post actually clouds the FG operation a bit.  The voltage at the FG signal ground never changes potential.  The FG signal ground is always at whatever potential it is connected to.  In her case, the FG signal ground is always at the same voltage as indicated at the non-battery end of the CSR, to which the FG signal ground is connected.  I know you know this, but I want this to be very clear.

I wish someone would post a drawing depicting two batteries in series with the common center of those two batteries connected to the non-battery end of the CSR.  An spdt switch would then have its throws connected to each battery free end and the pole connected via a series connected 50R to the Q1gate/Q2 source.

When the switch is in one position, a positive voltage is applied to the gate of Q1 and to the source of Q2.

When the switch is in the opposite position, a negative voltage is applied to the gate of Q1 and to the source of Q2.

This would be a very accurate representation of the action of the FG in this circuit.

Maybe then she could visualise the action of the FG in her circuit and how Q2 is biased on.

But then, maybe not...

PW

TinselKoala

Voltages are relative, though. It is clearly possible for a voltage to be applied that is "below" or more negative than the signal ground, as your SPDT switch example proves. Then, if one attached the negative lead of a voltmeter to that more negative voltage, the signal ground would be positive with respect to it, and if you put a circuit element in there, current would flow in the proper conventional direction wrt the signs of the measurement. How's that for clouding the issue?

The voltage at the (FG signal ground-system ground-Q2 gate) never changes potential, that is true, but "voltage" is potential with respect to-- or reference to-- another potential. What happens is that the "other" FG wire swings positive _ and negative_ with respect to that fixed reference level. So if you have your voltmeter's negative lead hooked to the signal ground, it will appear to indicate both positive and negative polarities as the other lead swings.So when you are applying a voltage to the Q2 source that is more negative than the common ground (where the Q2 gate is hooked up), that makes Q2's gate _positive with respect to Q2's source_ even though that point is pinned to the system and signal ground potential. The transistor then moves in and out of the linear conductance region as the FG's negative signal to the source (hence the positive relative signal to its gate) fluctuates around that 4 volt potential difference level during the oscillations. (Of course here we are treating the csr as if it weren't there or that the FG's ground is connected as in the demo video, not the schematic.)

We are both describing the same thing, and agreeing about it, but just from different perspectives.