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Overunity Machines Forum



Testing the TK Tar Baby

Started by TinselKoala, March 25, 2012, 05:11:53 PM

Previous topic - Next topic

0 Members and 113 Guests are viewing this topic.

fuzzytomcat

Howdy members and guests,

Quote from: Rosemary Ainslie on July 03, 2012, 04:21:40 AM
And Guys,

Here's yet another answer.  This time related to our 'schematic' which MOST ASSUREDLY was NOT correct.  But there is nothing in the history of these threads of mine or threads about me and our work - that requires the KIND of disclosure that TK seems to think that I am beholden to given him.  Frankly - neither he nor anyone of those who contribute so diligently here - can demand ANYTHING AT ALL  of me in the light of their multiple and legal abuses of calumny malice and slander.

..... snip rubbish .....

Kindest regards,
Rosemary


Here is the posting from poynt99 with the confrontation on the claimed COP>INFINITY device operation schematic with the shown as built.


Rosemary Ainslie circuit demonstration on Saturday March 12th 2011

Quote from: poynt99
http://www.overunity.com/10407/rosemary-ainslie-circuit-demonstration-on-saturday-march-12th-2011/msg282094/#msg282094      Reply #682 on: April 19, 2011, 08:01:26 AM 

Well, this is terribly embarrassing; According to their published circuit diagram, simulation diagram, and the demonstration video, Rosie-posie and her team of "experts" has not only incorrectly labeled two of the nodes on the prototype board (the F and C are incorrectly swapped), but they have connected mosfets 2-5 incorrectly as well (the Gate and Source pins are incorrectly swapped, but M1 is all correct). It is not surprising however that her "experts" didn't catch this big "OOOPS" when they were repairing the unit.

This would explain the somewhat funky wave forms, and why the simulation results look slightly different.

This sure doesn't instill much confidence in anyone following along with this travesty, especially when considering the entire project is already teetering on the brink of self-destruction. A rhetorical question or two; So what are we now to make of all those posted wave forms and so-called measurements? Are the probes even displaying the circuit nodes we have been led to believe they are displaying?

That aside, as a gesture of good faith Rosie-posie, may the world please see that properly-conducted continuous operation test? I'm afraid it's the only way you're going to prove to anyone beyond a reasonable doubt that your claims are true.

Quote from: Rosemary Ainslie
http://www.overunity.com/10407/rosemary-ainslie-circuit-demonstration-on-saturday-march-12th-2011/msg282102/#msg282102    Reply #685 on: April 19, 2011, 09:05:14 AM

You've got a long wait Poynty Point.  LOL.  All I concede is that there is - indeed - a modification to the positioning of the Gate and Source pins.  We made full disclosure - but I was rather hoping you'd try those replications - and then explain what was required.  It would have been a delicious opportunity to 'teach' you as I'm rather sick of being 'taught'.  But be that as it may.  The results persist.  It's an advantageous arrangement - AND - you see for yourself - it gives us an oscillation that is EXTREMELY BENEFICIAL.  That's all that matters.

I will admit that I did not expect you to pick up on this.  LOL.  I just wondered how you managed all those Spice replications.  I had an idea you must have seen this then.

Take care Poynty. I admit to being trumped.

Rosie-posie.



Rosemary's quote of "We made full disclosure"was never done and no link providing proof has been provided by Rosemary prior to the above posting by poynt99 on April 19, 2011

After the proof in the above postings what Rosemary did isn't  scientific misconduct bordering on outright fraud, in my opinion it's crossed that boundary.

FTC
???

Magluvin

Quote from: Rosemary Ainslie on July 03, 2012, 04:21:40 AM
And Guys,

Here's yet another answer.  This time related to our 'schematic' which MOST ASSUREDLY was NOT correct.  But there is nothing in the history of these threads of mine or threads about me and our work - that requires the KIND of disclosure that TK seems to think that I am beholden to given him.  Frankly - neither he nor anyone of those who contribute so diligently here - can demand ANYTHING AT ALL  of me in the light of their multiple and legal abuses of calumny malice and slander.

http://www.energy-shiftingparadigms.com/index.php/topic,2311.msg2466.html#msg2466

Kindest regards,
Rosemary


Wow, so she is now saying that these circuits are not correct? Circuits that she has argued on her behalf?  This just gets weird.

Mags

picowatt

This is a quote from her in response to TK asking about .99's drawing depicting an FG output connected to the NERD circuit:


"On the whole I agree with this.  But there's a small distinction.  The function generator can ONLY pass current to and from the plug that powers it.  It can only INDUCE current elsewhere.  The distinction is critical. Our oscillation is able to induce upwards of 8 amps.  There are at LEAST R50 Ohms in series with its probe and terminal.  Therefore. In order to deliver 8 amps the function generator would need to find that energy from a voltage upwards of 400 volts.  Frankly if any function generator delivered even half that amount of energy it would be deemed to be catastrophically compromised and would be sent off for repair.  It's ABSURD to suggest that the function generator is responsible for that level of current flow.  And its absurdity is ever greater as we can only measure a maximum of 6 volts AC from its signal.  Therefore not only is the proposal that the function generator is responsible for this extra energy - theoretically IMPROBABLE - it is also lacking in MEASURABLE EVIDENCE"


It is, as usual, dificult to understand what she is attempting to say regarding some distinction she is trying to make about an FG's ability to only INDUCE current elsewhere.

Referring to .99's depiction of the FG output, the FG power supply is _identical_ to two batteries connected so that the FG output transistors can alternately select between connecting the "upper" battery to the output or the "bottom" battery to the output.  This allows the FG to output a positive voltage or negative voltage relative to its signal ground when the upper or lower output transistor is turned on.   The FG acts identically to a battery in series with a 50 ohm resistor, and the polarity of that "battery" is determined by which transistor is turned on in the FG output stage.  The only true difference between a "real" battery and those represented as being contained in the FG power supply, is that the FG power supply constantly "recharges" the "batteries" depicted in the .99's FG drawing.  Obviously, a battery operated FG would draw from its batteries and not be recharged.

When the FG in .99's drawing is set to full positive offset, its output will be approx +14 volts.  That is, the upper transistor will be turned on and the FG's internal positive "battery" is connected to the FG output (the output transistors have an inherent voltage drop when they are turned on so only 14 volts or so will be output instead of the full 15.5 volts of the supply).

When the +14 volts is connected to the NERD circuit, +14 volts is applied to the gate of Q1 and source of Q2.  Q1 turns on and Q2, being reverse biased, remains off.  The only current flow thru the FG under these condicitons is Q1 and Q2 leakage current, which is very low, typically a few nanoamps or less.  Due to this very small current flow thru the FG, there is very little voltage drop observed across the FG's internal 50 ohm resistor (i.e., the Vdrop across Rgen is .5uV or less).   
   

When the FG in .99's drawing is set to its full negative offset, that is the lower transistor turned on and the negative oriented (lower) battery connected to the FG output, it is a bit more complicated than the positive instance.  If the FG is disconnected from the circuit, that is, measured "open circuit", there would be approximately -14 volts measured at its output.  When this -14volts from the FG is connected to the circuit, the negative voltage applied to the source of Q2 and gate of Q1 causes Q2 to turn on and Q1 to turn off.

However, when Q2 turns on, significant current flows thru the FG's 50 ohm resistor and because of this, a voltage drop is observed across the 50 ohm resistor.  It takes around -4 volts applied to the source of Q2 to begin to turn Q2 on significantly.  Q2 cannot, however, turn completely on as the voltage drop across the 50 ohm FG resistor due to Q2 current flow causes the voltage applied to the source of Q2 to decrease.

As Q2 attempts to draw more current, the voltage drop across the FG's 50 ohm resistor increases and therefore the negative voltage applied to the source of Q2 decreases.  This action is very similar to that of a current limiter and, therefore, the current flowing thru Q2 and the FG when the FG output is negative voltage, will be determined by the Vgs(on) of the MOSFET, the 50 ohm FG resistor, and the open circuit voltage of the FG.

In the above example, with the FG set to an open circuit voltage of -14 volts and a MOSFET Vgs(on) of -4 volts, there will be 10 volts of voltage drop across the 50 ohm resistor.  Using Ohm's law, we can see that 10V/50R=.2 amps, or 200 milliamps.  Therefore it can be predicted that when the FG is set to its full negative offset, there will be approximately 200milliamps flowing thru Q2 and the FG to the CSR.  This 200milliamps of current flow is referred to as "bias current", or simply Ibias.

It must be stated that the predicted bias current under the above conditions is only approximate, as the turn on characteristics of a MOSFET are quite variable, varying between devices and with temperature.  But regardless of the amount of negative voltage the FG is set to output, once the negative voltage from the FG exceeds the Q2 threshold voltage, there will be little further change in the voltage measured at the source of Q2, it will always be very close to -4volts within +/- 1volt. 

If the FG is set to produce -10 volts open circuit, again, the measured voltage at the source of Q2 will remain close to -4 volts, and 6 volts will be dropped across the FG's 50 ohm resistor due to Q2 current flowing thru it, and again, using Ohm's law, we can predict the bias current to be 6V/50R=.120 amps, or 120 milliamps under these conditions.

It should therefore be appreciated that once the FG's output exceeds -Vth, or approximately -4 volts, the voltage at the source of Q2 will change very little, and only the bias current flowing thru Q2 and the FG will increase as the FG output is made more negative. 

This voltage clamping action predicted at the source of Q2 is readily apparent in all of the provided captures, and it has been simulated as well as empirically observed and measured.

In all the captures she has provided, it can be readily seen that during the portion of  FG cycle wherein the FG output is a negative voltage, the voltage indicated by the FG trace never exceeds Vgs(on), or about -4 volts and is direct evidence and proof of current flow thru Q2 and the FG to the CSR.

(assuming of course that the FG common is connected to the CSR and not the battery negative.  If the FG common is connected to the battery negative terminal instead of the FG, the Q2 bias current will bypass the CSR and flow diretly to the battery negative terminal)

ADDED:  It should be noted that if a low impedance tweve volt battery (such as a lead acid battery) were connected so that its positive terminal were connected to the NERD battery ground and its negative terminal connected directly to the gate of Q1 and source of Q2, without a series current limiting resistor, Q2 would turn fully on.  There would be no oscillations, but the observed DC current flow would exceed the maximum Q1 current when it is on, as Q2 is actually 4 MOSFETs in parallel and their combined Rds(on) would be 4 times less (approx .5 ohms).  In this "fully on" condition, Q2 would now be acting as a switch and would not be biased into linear operation as an amplifier as happens when the 50 ohm series resistor is present.   

picowatt

And in continuation, again here is her quoted response:

"On the whole I agree with this.  But there's a small distinction.  The function generator can ONLY pass current to and from the plug that powers it.  It can only INDUCE current elsewhere.  The distinction is critical. Our oscillation is able to induce upwards of 8 amps.  There are at LEAST R50 Ohms in series with its probe and terminal.  Therefore. In order to deliver 8 amps the function generator would need to find that energy from a voltage upwards of 400 volts.  Frankly if any function generator delivered even half that amount of energy it would be deemed to be catastrophically compromised and would be sent off for repair.  It's ABSURD to suggest that the function generator is responsible for that level of current flow.  And its absurdity is ever greater as we can only measure a maximum of 6 volts AC from its signal.  Therefore not only is the proposal that the function generator is responsible for this extra energy - theoretically IMPROBABLE - it is also lacking in MEASURABLE EVIDENCE."



Her argument that the FG cannot pass all of the observed AC current is quite sound.  Any DC or AC current flow thru the FG to the CSR will be limited by the 50 ohm resistor in the FG's output path.

But, as I am apparently psychic, I explained the major AC curret path in my reply #3573.

There is approximately 2000 to 2500pF of capacitance between the gate and source of an IRFPG50 MOSFET.  If one looks carefully at the circuit schematic, it will be apparent that all 5 of the MOSFET's gate to source capacitances are electrically connected in parallel and provide a path for AC current flow directly to the CSR.

These 5 parallel gate to source capacitances, totaling 10,000 to 12,500uF (10 to 12.5nF) provide an AC current path directly across the FG's output terminals allowing AC current to bypass the FG.

(If you draw in an 8000pF cap between the source and gate of Q2, and another 2000pF cap betwee the source and gate of Q1, representing the MOSFET gate to source capacitances, this will be more easily visualized in the schematic)

If the oscillation were a pure sine wave, this 10nF or so of capacitance has a reactance at 1.5MHz of approximately 10 ohms.  This means that not only is there an AC/DC path of 50 ohms thru the FG, there is also an AC only path in parallel with the FG output terminals equal to 10 ohms.

So, for AC currents at 1.5MHz (of a pure sine), there is a 50 ohm path in parallel with a 10 ohm path, or approximately an 8 ohm path, from the source of Q2 to the CSR. 

It must be noted that the observed oscillation is not a pure sine.  Although its fundamental may be approximately 1.5MHz, there is a large amount of observed harmonic distortion.  An FFT of the oscillation signal would show that there is a substantial amount of even and odd harmonics present, with the third harmonic likely being the most significant.  These harmonics are higher in frequency than the fundamental (they are, afterall, "harmonics") and to these harmonics, the 10nF effective capacitance across the FG terminals represents a much lower impedance path to the CSR than it does at the fundamental frequency.

Any second harmonic present in the oscillation waveform will see the reactance of the 10nF capacitance across the FG terminals as though it were a 5 ohm resistor.  For any third harmonic present, this path would equate to a 3.3 ohm resistor. 

It should be appreciated, therefore, that although the DC and AC current that can flow thru Q2 and the FG is limited by the FG's internal 50 ohm resistor, the gate to source capacitance of the five MOSFET's, being electrically connected in parallel across the FG output terminals, provides a very significant low impedance path for AC current flow thru Q2 to the CSR.     

TinselKoala

Thanks for that excellent analysys, PW.  (Crossed posts, I am mostly referring to the first part of your analysis)

That last point -- about the FG's black lead location --  is particularly important as it affects the data taken. In the Video Demo, and presumably in the experiments described in the "papers" -- since they were done with the demo apparatus but BEFORE the true schematic was revealed by .99 -- the FG's black clip was connected to the common ground bus on the pegboard, connected directly to the battery negative. 

However, after some discussion of the issue it was decided that the CVR "should" be first, and that the FG's black clip should be connected between the CVR and the transistors, to put the CVR into the FG's current loop.

And magically.... the new diagrams in the papers reflected this correct location -- when at the time the experiments were performed she did not know the true schematic at all ... or did she? ..... Well, what did she know and when did she know it?

Were the experiments done that correct way, or the way the demo was done? I think I know.

So the FG connection in the video wasn't a "one time error", was it. I think it was the way all the experiments reported in the papers were done as well: in other words, the schematic given in the papers is STILL A LIE in that it does not reflect the true location of the FG's black clip connection during the performance of the trials reported, and all the Current data are IN ERROR because they do not include this FG bias source current flow which is ultimately part of the current flowing in the load. And of course conclusions based on erroneous, false or incorrectly obtained data are not valid.


Presently, she apparently has still not watched my FG passing current videos  to see that in a single series loop, the external battery's full voltage is indeed passed along through the FG to run small loads in perfect conformance with Ohm's Law and Kirchoff's circuit rules. Or perhaps she has and is attempting to understand their application to her problem.
Perhaps... due to her lack of careful thought and general rush-to-judgment, coupled with her continued profound lack of understanding of her own circuit... she believes that I am suggesting that the ENTIRE BATTERY CURRENT must flow through the FG IN HER CIRCUIT.... which of course contains two parallel current loops, not one. MileHigh has, I believe, detailed these current loops quite well in various drawings that Ainslie ignores or fails to comprehend. Of course I am not and have never suggested that at all, under the normal operation of the circuit.

When Q1 is OFF there is only the small current being passed by the Q2 oscillations going through the FG. When Q1 is ON its low-impedance drain-source channel conducts the large nonoscillating DC current. Only if one or more Q2s are shorted D-S (or deliberately turned on) will the FG be in a low impedance path directly in series with the battery. And even then it is difficult to come up with the current values Ainslie arrives at. Say my F43 is putting out, or trying to, its full -20 volts, but the voltage clamp keeps the voltage at -4 and the FG is sourcing considerable current for the oscillations, and is in series with the main battery. SO the total voltage between the Q2 source and drain is 72+20 = 92 volts, or would be if the circuit was open. Now short-circuit the Q2. We still have the 50R series impedance of the FG and the 11R of the load, so the most current that will flow through the FG is still 92/61 = quite a bit less than 2 amps.

Now...of course.... when I was driving a load with essentially zero resistance and a lot of inductive reactance with her circuit and the mosfets shorted from reflected power.... THEN my FG WAS placed in the primary current loop and the full 72 volts of the battery supply I was using was placed across the FG's output without the restriction of a load resistance ... briefly. And the expected result resulted as expected.  Unfortunately this fast voltage rise and current surge exceeds the power dissipation ratings of my F43's output transistors, which as .99 has shown, are also in this FG output loop. Therefore they (or rather one of them) failed, causing the FG's line fuse to blow.

However this mode of "operation" has not ... except for one time that we know about ... been applied by Ainslie to her circuit. (Remember the cluster of reports "batteries catch fire", "apparatus still not working", "function generator replaced", "two mosfets replaced" etc.)

Interestingly, in my recent AC/DC coupling demonstration, one can see the very same voltage floor effect happening. The supply voltage is 12 volts, but the gate never goes more than half a volt on either side of +4 volts. (Or, to put it another way, the _source_ voltage varies by half a volt around -4 volts wrt the gate.)  The gate charge reservoir capacitor cannot charge much over 4 volts before the relay actuates and removes the charge path and establishes the discharge path... and when the cap voltage drops a bit below 4 volts and the mosfet, falling through its linear conductance region, turns off and the relay relaxes, the charge path is reestablished and the voltage rises to just over 4 volts and the mosfet turns on again and the relay actuates...... The oscillation mechanism is essentially the same as in the Ainslie circuit, just in the NERD circuit the capacitances are much much lower (therefore things happen faster). The important point is that the gate-source voltage difference cannot go far from 4 volts, even though the supply is 12 volts--- or 24 or 48, etc. because when the mosfet turns on the gate voltage falls below 4 v and the mosfet turns off again allowing the gate voltage to rise above 4 v .....