Kapanadze Cousin - DALLY FREE ENERGY

[verpies]

What do you think about the oscillations at the blue drain when mosfet is conducting?
Why do you think now my gate signals are spiking like that?

I don't think these spikes are real. 
If you actually had such voltage spikes on the gate, your MOSFETs would be dead already.

They seem to be measurement artifacts, e.g. due to poor grounding or power rail decoupling..

[Farmhand]

Good day all:

Just wanted to post some very interesting reading material: If you want to really get into the basic mechanisms involved with coil resonance(s), I have attached an U.S. patent from March of 2010 dealing with *double* resonant systems, or as some say 'resonance within resonance'.
This is some of the *BEST* reading material I have come across with a plethora of information in one document. You might want to read it a number of times to actually grasp the scope of application........  I believe that this is what applies to the D.S. replication and probably has applications in relation to the Ruslan device as well.

I find very interesting the differentiation between L/C resonance and 1/4 wave resonance........  this patent give an iterative development cycle /method (actual steps involved) of combining the two resonances in one coil for the *preferred* results.

enjoy........

take care, peace
lost_bro

That is an interesting Patent Application for sure, just reading the abstract is enticing. Are you planning to experiment with such an arrangement ? Seems like an interesting thing to mess with. It's a largish document, will take some reading. Cool.

Umm. I see the Applicants name is Patrick D Kelly. Wondering if it is the same Patrick Kelly from the Free Energy devices book.
Oh and the application is from 2010. No actual Patent granted yet ?

P.S. I think Tesla's "Coil For Electro-Magnets" Patent covers what he claims not to know of below.

[0083] The Applicant herein is not aware of any prior
devices that combine both types of resonant behavior (i.e.,
standing-wave resonance, and L/C balance resonance) into a
single circuit element.

..

[Jeg]

I don't think these spikes are real. 
If you actually had such voltage spikes on the gate, your MOSFETs would be dead already.

They seem to be measurement artifacts, e.g. due to poor grounding or power rail decoupling..

I'll check again in case i missed a connection or something.
What about the initial peak? Does it look normal? It supposed that it would be recycled back to the pwr sup. As for diodes i used an mbr10200 double schotty in one case.   
I used 330uF electrolytic caps connected at the drains in parallel with a 100nF ceramic cap.

[verpies]

I'll check again in case i missed a connection or something.

I suspect it is a matter of layout more than a bad connection.
Every long wire is an inductor, all large current loops behave as coils (see the purple loop in the diagram attached below).

Do you use starpoint grounding scheme? Do you glue the MOSFET drivers right to the MOSFETs ?  Do you have separate voltage rails with separate regulators that are choked and bypassed with low impedance caps at these frequencies?

What about the initial peak? Does it look normal?

No, it should be clamped at 2*V_CC.  Did you follow the dot convention of the primary windings?

Also, there should be no spikes in the gate waveform, ...especially in the middle of its period.
Did you glue the MOSFET drivers right to the MOSFETs like Itsu?  Did you bypass their power supply pins with a cap soldered right across them?  (see the purple capacitor in the diagram attached below).

It supposed that it would be recycled back to the pwr sup.

It will be when the spikes become clamped at 2*V_CC.

As for diodes i used an mbr10200 double Schottky in one case.   
I used 330uF electrolytic caps connected at the drains in parallel with a 100nF ceramic cap.

As long as these diodes are fast (Schottky are) and capable of withstanding 2*V_CC reverse voltage, then I have no objections to them. 
The caps should be fine, too.  Measure an make sure that the voltage across them is DC equal to 2*V_CC most of the time.  This measurement will confirm that you have correctly followed the dot convention of the primary clamp windings on the schematic and that diodes are polarized correctly.

[Jeg]

Do you use starpoint grounding scheme? Do you glue the MOSFET drivers right to the MOSFETs ?  Do you have separate voltage rails with separate regulators that are choked and bypassed with low impedance caps at these frequencies?

No starpoint. I'll see if i can change it.
Mosfet driver (ir2110) is connected with about 20cm cables to its pins.
Yes, my regulators are bypassed

No, it should be clamped at 2*V_CC.  Did you follow the dot convention of the primary windings?

Yes i followed the dots.

Also, there should be no spikes in the gate waveform, ...especially in the middle of its period.
Did you glue the MOSFET drivers right to the MOSFETs like Itsu?  Did you bypass their power supply pins with a cap soldered right across them?  (see the purple capacitor in the diagram attached below).

Yes, a 100nF right across driver's Vcc and gnd.

Measure and make sure that the voltage across them is DC equal to 2*V_CC most of the time.  This measurement will confirm that you have correctly followed the dot convention of the primary clamp windings on the schematic and that diodes are polarized correctly.

I will measure it asap and report.

Thanks