Kapanadze Cousin - DALLY FREE ENERGY

[NickZ]

Conico that is a very nice PCB card you have there I don't suppose you have a photo of the back side of the PCB I can copy and put on here ? any help would be appreciated by all I'm sure.

AG


  Yea, conico, nice work, and can you make me a nice assembled board like that one, also. So, that I can show it on here, as well?
   As Geo didn't reply to my suggestion of having one like his made for me. So... I keep trying...

[apecore]

But Guys,


Lets get to buisiness......or i will also go and sit back waiting for the burried selfrunner

How about try too tune until the effect and then start eliminating the distortion on the gates.......

This must be simple by adding some small snubbers on the gate/drains?

We need also some reference pictures wich tells us what distortion on the gates is accepted or normal at operating on full power.
Lets see if we get some degradation of effect/ or else wich again can be discussed and what will lead to close the never ending discussion about the effect cause

[verpies]

Over voltage on the mosfet gates is not every ones problem, nor the only cause of component burn outs. I don't see any of these problems on my own set up, nor excessive heating of the fets, either. 
I don't think over voltages on the gates are the way to achieve free energy, at all. Nor do I see any one else thinking that as well. So, I don't know where Verpies is getting those ideas from.

There is a small step from gate interference to gate overvoltage.

Gate overvoltage is the extreme scenario and I am happy for you that you do not suffer from it. 
The more moderate and more common scenario is sub V_{GS_MAX} gate interference, in which the HV spike is not sufficient to damage the gate, but is capable of being amplified by the MOSFET and spuriously switching the drain circuit....and whatever is in it.

If anyone is seeing over voltages on their gates, this does need to be addressed, of course, but the circuit and snubbers to avoid this from happening are already known, and posted, if people would just follow the schematics. Yet no one does, and chose to invent their own snubbers systems, instead, which may cause these types of problems.

Please do not conflate the gate protection circuits with drain protection circuits.

I am not advocating totally suppressing HV spikes in the drain circuit, if they do not exceed the maximum Drain-Source voltage rating of the MOSFET.  In other words, to protect the MOSFETs, the drain circuit spikes must be suppressed below V_DS Max and below Max drain dv/dt,  ...but that does not mean all the way down to zero.
Also, I am not proposing isolating the grenade inductor and yoke transformer from the influence of HV HF electric fields.  Let them bathe in it, for all it's worth.

I am a proponent of immunizing the gate control circuits from the HV interference and preventing any spurious MOSFET switching, that is not explicitly ordered by these control circuits.
Starting with gluing the MOSFET drivers to the MOSFETs and shielding, choking, bypassing the entire gate control circuit.

[verpies]

You're lucky you didn't ban me completely.

Loose minds like Jbignes5 and Meta are repugnant to me, thus I ad-block them and do not even reply to their posts.

[apecore]

There is a small step from gate interference to gate overvoltage.

Gate overvoltage is the extreme scenario and I am happy for you that you do not suffer from it. 
The more moderate and more common scenario is sub V_{GS_MAX} gate interference, in which the HV spike is not sufficient to damage the gate, but is capable of being amplified by the MOSFET and spuriously switching the drain circuit....and whatever is in it.
Please do not conflate the gate protection circuits with drain protection circuits.

I am not advocating totally suppressing HV spikes in the drain circuit, if they do not exceed the maximum Drain-Source voltage rating of the MOSFET.  In other words, the drain circuit spikes must be suppressed below V_DS Max and below Max drain dv/dt,  ...but that does not mean all the way down to zero.
Also, I am not proposing isolating the grenade inductor and yoke transformer from the influence of HV HF electric fields.  Let them bathe in it, for all it's worth.

I am a proponent of immunizing the gate control circuits from the HV interference and preventing any spurious MOSFET switching, that is not explicitly ordered by these control circuits.
Starting with gluing the MOSFET drivers to the MOSFETs and shielding, choking, bypassing the entire gate control circuit.

Verpies,

Attached pictures are the fet signals generated by 5Amps.
Kacher is on with spark gap ( so likely most possible interference)

This is in my perception a much cleaner signal as i had months ago,... doing the Hoppy test on the video.
Is this acceptable in case of fet distortion ,...... btw:... i have no effect

Just powering 3 bulbs 100W in series with 1 volt RMS true a 1.2Ohm resistant.... So i guess i have 1 Apm RMS true my load
RMS voltage across the bulbs is 67V
Pushpull takes 4amps and the kacher 1.5Amps
2 batteries 12 Volt gives 24 volt

So input pushpull 88Watt
Kacher 36Watt
And output 67Watt