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Overunity Machines Forum



Kapanadze Cousin - DALLY FREE ENERGY

Started by 27Bubba, September 18, 2012, 02:17:22 PM

Previous topic - Next topic

0 Members and 106 Guests are viewing this topic.

dorcky

Quote from: verpies on October 21, 2012, 03:59:31 AM
So as you are increasing the pulse width (increasing the effective resistance at R12) using the monostable made out of U3, the pulse width suddenly increases from 500ns to 20us. Correct?

This is most likely caused by the inability of the resistance at R12 to drive the input to the NAND gate at pin 5 of U3.
this would happen even if C17 was removed, because the input to the NAND gate requires significant current and R12 limits this current.
Input impedance is not a problem is C/MOS logic but it is a problem with TTL logic ICs.

The solution to pulse widths greater than 500ns is the increase of the swappable capacitor C17, however that will affect your minimum pulse width if you do not decrease R12.

Hello verpies!

Off Topic!
Thank You for every useful infos that you are bring to us... I learn very much things from you till now, hope you will stay with us and share more of your knowledge...

ON Topic!
I see that you are using some personalized names for caps and resistors witch I cannot find on original schematics. Can you give us more detail, or maybe a redrawn schematic?

My best regards!

verpies

Quote from: dorcky on October 21, 2012, 01:58:39 PM
I see that you are using some personalized names for caps and resistors witch I cannot find on original schematics. Can you give us more detail, or maybe a redrawn schematic?
I refer to component designations appearing in the schematic attached to Reply #274.

verpies

Quote from: itsu on October 21, 2012, 06:12:50 AM
Correct, see last part of the video, so no other options then to stay within this window (37-500ns) and try to increase the number of turns on the primary for trying to find the saturation point of the toroid.
To understand why your duty cycle "jumps up" from 1% to 55%, ask yourself this question:
What is the logic level of an unconnected input in a TTL logic, e.g.: a NAND gate?

Then realize that when the input is connected through some high kΩ resistor, then it is treated by the TTL logic the same way as an unconnected input.

If the monostable multivibrator (now U3) was made out of NOR gates it would not suffer from this "jumping up" problem.

verpies

Quote from: itsu on October 21, 2012, 05:58:50 AM
Oops,  i guess you are right,  sorry about that,  anyway here the video:
http://www.youtube.com/watch?v=PxdoLkw1Fbs
I watched the video.
Very sharp pulse shapes :)

I was missing the scopeshot across the CSR when the primary of T1 was connected in series with it.
It would be interesting to observe how the primary current increases as you increase the driving pulse width.

d3x0r

So... transistors don't work as I thought they would.  I figured; since I blew up my NTE part that had a really short storage/recovery time, I have a half-cycle unused on the second TL494, so I figured I could use that to do transfer some of the 150V into the near capacitor, which would be used when the other side fires... but then it would only use what was in the cap, not the whole 20us of current it could get to before...


but, applying signal to the gate only allows the voltage equal to the gate to be on the emitter... it's not a relay, huh?