Kapanadze Cousin - DALLY FREE ENERGY

[Hoppy]

  Hoppy and Itsu:
  I remember the increase in power that both you and Itsu had previously shown. HOWEVER, that is no where the same increase as what is being shown by this last Russian guy, (I forget his name).

Nick,

Incorrect. The increase was dependant on me tuning the Kacher with a ferrite rod, as that guy Ypok was doing. I could get the bulb really bright that way, up to almost 280V across the 240V rated bulb, bringing it close to blowing out! However, as mentioned before, this was at the expense of more supply current and therefore not the power amplification effect that T1000 is talking about.

[Tomtech29]

Here a zoomed in screenshot of the firing of the kacher (purple) ontop of the current peak (green).
Gate pulse is at its maximum width and narrowing it down decreases the kachers amplitude
The kacher runs/rings at 1.28MHz, see top right purple delta data.


Regards Itsu

nice work if you can do something with this bell get sharp edges or high-voltage seen something on the bulb?
if you checked the performance of the winding 28 out?

[itsu]

Taking a look at the kacher output with my HV probe (x1000).
I connected it to the open end of the antenna which will load the kacher to some extent presenting a lower frequency and amplitude, but it shows somewhat what we are up against.

Certainly no 26KV or wavefront peak as drawn by akula/ruslan....yet.


Regards Itsu

[verpies]

Introducing bigger cap lets you give more time for delay but also you need to be aware of catch 22 situation if your PLL trigger input is still on the peak of voltage. The time delay you set on pot will not match time delay between voltage and current peaks if the frequency will change too much.

You are correct but I don't see how the PLL could not be synched to voltage if it is transferring energy to the LC circuit (Grenade) from AC voltage sources (switched MOSFETs).

[starcruiser]

Hi itsu,

Introducing bigger cap lets you give more time for delay but also you need to be aware of catch 22 situation if your PLL trigger input is still on the peak of voltage. The time delay you set on pot will not match time delay between voltage and current peaks if the frequency will change too much.

I do not think so as the trigger signal is take from the drive signal from the PLL to the Fets for the 15Khz push/pull. SO if the frequency changes the pulse should follow. But you may be correct now that I think about it, but this would always be the issue anyways.

The issue I am concerned with is the fact the more capacitance means it should take a few more cycles to reach trigger point for the logic gates, i.e. t increases. this can be verified by probing the drive signal in the logic gate chain (see capture below) scope the output of the NAND gate against the drive signal, I figure we are seeing a multiple cycles to a signal to the next stage transition signal. like a 4:1 or something like that.

I circled the drive signal sample point after the 3.6k resistor and a blue circle after the second NAND stage.