Exploring the Inductive Resistor Heater

[picowatt]

Generally "yes" up until your last statements (3).  I said the draw-down test will give you 'some but not all' of the information you need to determine the input 'power' of the circuit. I did not say that this 1st draw-down test would give you THE input power.  Also you sited the 3.09, 3.099 values. Those only relate to the DC draw-down in which case the SH3 values are extremely accurate and reliable. So you were only correct in your understanding up until (3).


It's clear that you are still hung up on using real-time power values to determine efficiencies ... and you are wrong to assume that's correct with these types of circuits.


So, 'no', I'm afraid you still don't 'get it' and I've answered the "why" since that posting and posted jpegs from the slide show.


gme

Greg,

So, all is well regarding my understanding of step 1 and 2.  You seem to be saying I am incorrect about step 3, but are you actually saying that my understanding of the tests and measurements are correct, but only that you do not want that data to be used to calculate efficiency?  At least let me know I am grasping your test methods correctly.

So,again, is my understanding correct regarding your methods and measurements in step 1 thru 3?

If I am correct, but you are actually just "hung up" on not using any of that data "as is" to measure efficiency, fine, just say so and I can move on to step 4.

So, as I understand it, in step 4 you use the step 3 drawdown data (using the rheostat set for 5.6mv across SH3) and note the time it takes the battery to discharge to the step 1 end voltage (27.44V I think it was).  The step 3 drawdown reached 27.44V in less time than the step 1 test, so you use the shorter time interval of that drawdown to calculate the watt hours used in the step 1 BH circuit run.

Is this correct?

PW

[gmeast]

Another important note here regarding the Gate Driver: The power the gate driver is drawing either in-circuit or on its own support battery is NOT supplementing the HEATING of RL. Aside from its overhead from 'just being there', as it does its 'driver thing' the increase in power draw is from doing what it has to do to source and sink the current required in charging and discharging the gate capacitance in order to maintain the required gate charge voltage whether turning it 'ON' or 'OFF'.  This 'sourcing and sinking' is isolated from the rest of the MOSFET except for a leakage of 100nA ... 100 billionths of an Amp ... the published data for the UCC2732x drivers.


So, this is the reason why the gate driver's power is not considered in Exploring the Inductive Resistor heater. The ultimate goal is to have the components self-oscillate instead of relying on controlling circuitry such as a PWM and Driver arrangement ... something I've almost figured out how to do ... but not quite.


Everything is contained in that slide show, and in enough detail, to answer any and all questions. That's the reason I made it.  No more 'on the witness stand' "yes" or "no" questions ... capiche?


Regards,




Greg

[picowatt]

Greg,

Is my understanding correct up to and inclusive of step 4 in my previous post?

PW

[picowatt]

Another important note here regarding the Gate Driver: The power the gate driver is drawing either in-circuit or on its own support battery is NOT supplementing the HEATING of RL. Aside from its overhead from 'just being there', as it does its 'driver thing' the increase in power draw is from doing what it has to do to source and sink the current required in charging and discharging the gate capacitance in order to maintain the required gate charge voltage whether turning it 'ON' or 'OFF'.  This 'sourcing and sinking' is isolated from the rest of the MOSFET except for a leakage of 100nA ... 100 billionths of an Amp ... the published data for the UCC2732x drivers.


So, this is the reason why the gate driver's power is not considered in Exploring the Inductive Resistor heater. The ultimate goal is to have the components self-oscillate instead of relying on controlling circuitry such as a PWM and Driver arrangement ... something I've almost figured out how to do ... but not quite.


Everything is contained in that slide show, and in enough detail, to answer any and all questions. That's the reason I made it.  No more 'on the witness stand' "yes" or "no" questions ... capiche?


Regards,




Greg

Greg,

Your comments regarding the operation of a FET fall short of the true picture.  While it is true that under static DC conditions the gate leakage is typically very low, in the pico or nanoamp range, the dynamic conditions during turn on and turn off are quite different.

As you say, to turn the FET on or off the gate capacitance(s) must be charged or discharged.  To do this quickly requires a significant amount of current.  The driver you are using is capable of sourcing/sinking 4 amps for this purpose, but there are gate drivers capable of 20-40amps also available.

The most significant capacitances at the gate are the gate to source capacitance, Cgs, and the gate to drain capacitance Cgd.  Cgs is almost always the largest, and it is equivalent to a  capacitor connected between the gate and source of the FET.  Cgd is similarly equivalent to a capacitor connected between the gate and drain of the FET.  To charge Cgs from zero to 12 volts, the charging current must flow between the gate and source.  Simultaneously, to charge Cgd, charging current must flow between the gate and drain.  During hi speed switching, these charging currents can have very large peak currents.

If you are using the PG50, Cgs and Cgd are fairly large values.  From the data sheet you will see that Cgs and Cgd vary with the drain to source voltage, Vds, and when the Vds is near zero volts (as it is when the FET is turned on in your circuit for example), these capacitances are at their maximum value.  As the gate driver's waveforms typically contain a large amount of high frequency content (i.e., fast rise and fall times), the reactance of Cgs and Cgd can be quite low at these high frequencies causing large peak currents (many amps) to flow from the gate to both source and drain.  This is why a gate driver is typically used, to provide the amps of current needed to charge these capacitances rapidly.

In your circuit, however, you are limiting the gate drive current by using the 100 ohm resistor between the driver and the gate.  Assuming there is only small amount of stray capacitance between the driver output and the gate, whose reactance would effectively be in parallel with the 100 ohm gate resistor, your 100 ohm resistor limits the peak current available to charge the gate capacitances and hence greatly slows your on/off switching times as compared to what your driver is capable of.


It is a shame you are unwilling to discuss your circuit further.

PW

[gmeast]

Greg,

Your comments regarding the operation of a FET fall short of the true picture.  While it is true that under static DC conditions the gate leakage is typically very low, in the pico or nanoamp range, the dynamic conditions during turn on and turn off are quite different.

As you say, to turn the FET on or off the gate capacitance(s) must be charged or discharged.  To do this quickly requires a significant amount of current.  The driver you are using is capable of sourcing/sinking 4 amps for this purpose, but there are gate drivers capable of 20-40amps also available.

The most significant capacitances at the gate are the gate to source capacitance, Cgs, and the gate to drain capacitance Cgd.  Cgs is almost always the largest, and it is equivalent to a  capacitor connected between the gate and source of the FET.  Cgd is similarly equivalent to a capacitor connected between the gate and drain of the FET.  To charge Cgs from zero to 12 volts, the charging current must flow between the gate and source.  Simultaneously, to charge Cgd, charging current must flow between the gate and drain.  During hi speed switching, these charging currents can have very large peak currents.

If you are using the PG50, Cgs and Cgd are fairly large values.  From the data sheet you will see that Cgs and Cgd vary with the drain to source voltage, Vds, and when the Vds is near zero volts (as it is when the FET is turned on in your circuit for example), these capacitances are at their maximum value.  As the gate driver's waveforms typically contain a large amount of high frequency content (i.e., fast rise and fall times), the reactance of Cgs and Cgd can be quite low at these high frequencies causing large peak currents (many amps) to flow from the gate to both source and drain.  This is why a gate driver is typically used, to provide the amps of current needed to charge these capacitances rapidly.

In your circuit, however, you are limiting the gate drive current by using the 100 ohm resistor between the driver and the gate.  Assuming there is only small amount of stray capacitance between the driver output and the gate, whose reactance would effectively be in parallel with the 100 ohm gate resistor, your 100 ohm resistor limits the peak current available to charge the gate capacitances and hence greatly slows your on/off switching times as compared to what your driver is capable of.


It is a shame you are unwilling to discuss your circuit further.

PW

The driver I'm using supplies as much as 9Amps required to negotiate the challenges of the Muiller Plateau. The current is needed as I said it is and does NOT pass through to the drain. As I said the PG50 can only leak 100nA. My assessment does not fall short. I have had several good conversations with TI on the subject of the 321 firing the PG50 and you're all wet on this one. It's amazing how you clowns try and muddy the water when it comes to this Inductive Resistor Heater.


It's amazing how I start this thread and ass holes like you hikack it. FUCK YOU AND YOU TOO HARTMAN FOR LETTING THIS SHIT CONTINUE.