OU/COP>1 switched cap PS cct like Tesla's 'charge siphoning'

[Grumpy]

How is charge separation maintained in the dielectric? I have found experiments to determine if their are physical changes to the dielectric and there are none detected.  So, the mechanism is not the same as say a piezo crystal and that is mechanical anyway. 

I know what is going on, but haven't figured out how to prove it.

[poynt99]

What keeps the polarization in the dielectric is equal but opposite charge matching from within the plate itself (shortage or excess of electrons) at the surface junction with the vacuum. If you could remove the plates without disturbing the vacuum molecules in their precarious state (we also have to imagine that either other vacuum charges will back-fill where the plates once were, or charge is stripped off the plates as they're removed) ), there would still be two polarized, but invisible walls/regions present. This of course would be much easier to do if the dielectric core was a solid one, but the principle is the same.

No Physical change.

There will be a shortage of electrons on the negative capacitor plate (which is in close contact with the dielectric), and an excess of electrons on the positive plate of the capacitor (also in close contact with the dielectric). The metal capacitor plates themselves will be polarized as a result of this electron migration. Opposite charges attract, and it is this that retains the polarization of the dielectric.

Remove the metal plates and either charges from the surrounding vacuum spill in to fill the void, or they are stripped off the metal plates via electrostatics (charge exchange, triboelectric effect, charge induction) just as the plates are removed, or a combination of both.

.99

[alan]

and equal charges repel, also the reason for the separation in/over a cap.

[nul-points]

hi all

results of the first test are in - here's some context to the test...


the 2-stage test circuit transfers charges by first connecting the low-value switching capacitor, C2 to the input capacitor C1 via inductance L

as is well-known in SMPS design, this is a high-efficiency configuration, so we'd expect a high proportion of the charge removed from C1 to transfer into C2 for each pulse

charge from C2 is then switched to C3 via Rload (in this case 10ohm)

this is the point being tested: the regular 'textbook' treatment of capacitor charging (cf. example in quotes above from Texas Uni lecture notes) states that the amount of energy stored in a capacitor is equal in value to the amount of energy expended as work against the increasing polarisation of the capacitor dielectric


IF  this claim were true, then we could note the final stored voltage on C3 and double it to find the total energy converted by the system in the whole process

this was the basis for the original conclusions relating to my early tests with the 2-stage circuit: ie. since the final energy stored in C3 was greater than half the total input energy then double that amount would represent a net energy gain in the system - ie. overunity


the limited equipment i had available at that time only allowed for measurement of the final stored voltage on C3

so now that i'm able to measure both the input and output simultaneously i've repeated my earlier test to see if the 'textbook' claim is true

i've been able to replicate the situation where the final stored energy on C3, 21.5mJ, is greater than half the total input energy, 36.7mJ


so what's happening at Rload?

i measured the load waveform at the mid-point of input energy conversion - ie. 50% had been discharged, 50% still to go

the average power on Rload at this point was 4.9mW, giving a total charging power draw of 5.15mW when including dissipation from the 0.5 ohm DC resistance of L

the duration of the test run was 3.25s so the total charging energy was approx 16.7mJ


IF it was true that the final energy on C3 represented 50% of the total converted output energy, then the total WOULD HAVE BEEN 43mJ, representing an efficiency of 117%

however, i only got a value of 16.7mJ for the charging energy - so  IF  the 50% work relationship WAS true then there was still approx 5mJ** of energy unaccounted for

as the sum of the measured output energies, 38.2mJ, was so close to the input energy, 36.7mJ, i believe it's MORE LIKELY that the efficiency of the total system was just close to 100% (within experimental limits)


these results suggest that the 'textbook' claim is NOT a general rule - the work done in charging a capacitor DOES NOT have to equal the final energy stored - that's even WITHOUT a series inductor between C2 & C3

so - if there's NO 50:50 split in charging:stored output energy then it's likely there's NO OU here either - it's efficient - but probably not over 100% 

all the best
s.

[EDIT:  ** it's JUST possible that the 'missing' 5mJ could be accounted for in the noise produced by the coil and ferrite cores (an easily audible buzz during test)  but since i can't measure that, i can't include it in the results]

[nul-points]

[...continued...]


whilst running these most recent tests, i've uncovered a bug in the PC scope timebase software

running the test on one timebase shows a period of 95ms from start to reach approx 0.57v volt drop on C1; monitoring the same signal using a different timebase, supposedly displaying the same period from start, the C1 volt drop is only 0.39v

using a stopwatch & DVM readings i've been able to confirm that the PC scope timing is out by a factor of over 2x, when changing between medium and slow timebase ranges

the time values in question were displayed as the delta time between the sampling cursors, so they're being incorrectly displayed rather than misread!

you can see this in the Vin/Vout trace in the results just posted above - the actual duration of the test run was 3.25s - its displayed as approx 1.3s on the trace

happy days!


all the best
s.