Testing the TK Tar Baby

[TinselKoala]

PW said (and I agree):

Why is Q1 not turning on in FIG3 and FIG7?  During those captures, Q1 must must have been malfunctioning, disconnected, or not connected as per the schematic. 

It is almost as if Ainslie does not realize that those black lines in a schematic indicate wires, that the symbols G, D, and S have assigned meanings that don't move on the mosfet body, or that small changes in the positioning of wires or attachment points have non-negligible effects on circuitry.

There has been so much discussion about the simple depiction of a circuit using conventional schematics over the years that one would think that BY NOW, Ainslie would have learned to speak the language.

I mean... just look at the original Quantum schematic. Even my quick handdrawn sketches are better laid out and more conventionally organized than that mess. When did you EVER see a circuit using a 555 timer that specified the pin functions, but not the pin NUMBERS, on the schematic?

And that was a decade or more ago, and the present discussion.... Q2 source floating, Q1 source-Q2 gate not connected, and so forth..... shows that she STILL cannot read her own schematics properly...

-OR-

Perhaps once again she is NOT TELLING THE TRUTH about the ACTUAL SCHEMATIC being used in those scopeshots.


In other words, she's either a continuing, willfully ignorant idiot, or a mendacious liar engaging in pseudoscientific misconduct.... or, my favorite.... both.

[poynt99]

.99,

That is amazing that you found that line regarding Cgs in your Spice description, and that you actually looked/new where to look for it.  Great sim skills!

Thanks.

Can you do FFT's of waveforms in sim?

PW

Yes!

[poynt99]

So, are you saying that the burst envelope of the sim is slower than the NERD waveforms?

No. I am using a much higher burst control frequency on the order of 25kHz as opposed to the NERDs using a period of 2 minutes. As such, the burst envelope is more prominent when viewing the wave forms. I need to retain a minimum "sample rate" of sorts, so in order to stretch the sim out to much longer periods would require very long simulation times.

Next question, can you tell what values are being used for Coss in the MOSFET sims?

PW

No. The model is not that straight forward unfortunately. You might be able to derive Coss from the parameters they use in the model, but that is much beyond the level of analysis I wish to go.

MOSFET SPICE modeling has been a hot topic of debate for many years, and it is still in development. I believe there are models out there that account for the voltage-dependent capacitances, but they are not standard yet.

[poynt99]

.99,

Is this sim your single MOSFET burst osc or the NERD circuit?

What freq of osc did you end up with?

PW

It is the NERD circuit.

Without any added capacitance, Fo=1.59MHz.
With 2800pF C_GS for each MOSFET (2 total), Fo=1.47MHz.

[poynt99]

.99,

It looks like you should also have about 140pF gate to drain and about 110pF drain to source if you want to try putting Coss in there (if it isn't already) to see how that performs.  The Coss components are involved in feedback. 

Coss is specified to =250pF
Coss=Cgd+Cds        5% of Ciss=Cgd=140pF,  Cds=250-140=110pF

With Cgd=140pF, Cds=110pF, Cgs=2800pF per MOSFET, Fo=1.295MHz