Kapanadze Cousin - DALLY FREE ENERGY

[d3x0r]

Video here:   http://www.overunity.com/12736/kapanadze-cousin-dally-free-energy/new/#new

think you accidentally pasted the wrong link there

[verpies]

But still when adjusting upwards to 500  ns suddenly my MOSFET blows up.

What load is connected to the drain of your Q5 MOSFET now? 

If it's an inductor, then it not surprising that the Q5 MOSFET becomes overloaded at long pulse widths.
...but so what - 500ns is the upper limit of DSRD forward pumping anyway.

P.S.
I cannot find the newest video at your YouTube channel.

[d3x0r]

If it's an inductor, then it not surprising that the Q5 MOSFET becomes overloaded at long pulse widths.
...but so what - 500ns is the upper limit of DSRD forward pumping anyway.

is it?  I found on digikey and newark can sort by reverse recovery time, can go from 200us to 2ps... some say the speed of the swich is what's improtant?  should it be the pulse width?  200ns?  100ns?  50ns?


I find expiriments using diodes, but nothing describing what characteristic really deterimines effect...

[mihai.isteniuc]

This looks like the nano pulses I had from my original high speed 74HC00's [very fuzzy].  I replaced mine original with a different manufacturer's 74HCT00, and it was sharper, but now I'm using NTE 74LS00's, and the pulses were even more square... not so much grey/fuzzy after/before the pulses.   The noise was enough to trigger the transistor to conduct, and that was draining my 150 power very quickly, but with sharp pulses was able to maintain input power better; I'm not sure if mine is working, the parts came from a local store, but they are out of stock of both 74xx00's, and won'get get more until Nov 10

The pulses you are seeing were obtain before I realize I have a too long pulse. They where comming at 40-60 duty cycle from the low power nanopulser and an N channel mosfet as driver for the ring. This day I will make the modifications to see how it's gonna be with a low duty cycle. Also I'm thinking to make it adjustable like ITSU did...

Mihai

[verpies]

Found out that at  500ns ( duty cycle 1.4%) the pulse suddenly changes to a  duty cycle of 55%
Probably at that point my MOSFET blows up
Guess my modification to the n-pulser chip to use a cap of 220pF and 10K ohm trim pot is causing this.

So as you are increasing the pulse width (increasing the effective resistance at R12) using the monostable made out of U3, the pulse width suddenly increases from 500ns to 20us. Correct?

This is most likely caused by the inability of the resistance at R12 to drive the input to the NAND gate at pin 5 of U3.
this would happen even if C17 was removed, because the input to the NAND gate requires significant current and R12 limits this current.
Input impedance is not a problem is C/MOS logic but it is a problem with TTL logic ICs.

The solution to pulse widths greater than 500ns is the increase of the swappable capacitor C17, however that will affect your minimum pulse width if you do not decrease R12.