Rosemary Ainslie Quantum Magazine Circuit COP > 17 Claims

[TinselKoala]

As I predicted, Ainslie will not be pinned down as to the correct waveform to be used.

Any waveform that does not produce overunity is NOT the right waveform! So it's up to you to find it, silly, not for her to tell you about it. Just build something and tune it, take your pick of at least nine different circuits, and when you get overunity, THOSE are the right waveforms!

Don't try to make Glen's waveforms! They are something different, since he no longer agrees with Ainslie.

But at one time, she was very excited about Glen's waveforms, especially Test 3 and Test 13.

The first image is from today's posts. The second image is from Energetic Forum, October 6, 2009 -- before the falling out and the closing of that thread -- and refers to Glen's Test 3.

http://www.energeticforum.com/inductive-resistor/4314-cop-17-heater-rosemary-ainslie-97.html

And a few posts further on, after a lot of backslapping all around, and dissing the skeptics who have been censored away:
It cannot be said often enough.  You are truly amazing. Historically your efforts here must always be a primary reference.

[MileHigh]

The Great Turkey Shoot   

[poynt99]

Once again,

Here is the circuit I simulated. The position of the shunt resistor is located in series with the Source, but that is the only real difference, and was done as such because all Rose's and Glen's circuits are this way.

[TinselKoala]

I've seen that circuit before!  With the exception you note:

It is the power section of the Ainslie Quantum-17 article, of the "EIT" submission, of the IEEE submission and it is the Q1 portion of the 5-transistor NERD circuit. It is the power section of the circuit Ainslie tried to patent.

It is also the Unclamped Inductive Test circuit in the back of almost every N-ch power mosfet's data sheet, most especially that of the IRFPG50.... and it can also be found in the back pages of the IRFP450 mosfet as well.
As you know.

Interestingly, the data sheets also include the expected waveform at the DRAIN (Vds) and at the CURRENT MONITORING (Ias) point, when stimulated at the GATE by a rectangular pulse of duration Tp. And we find the notation to vary the pulse width in order to attain the required Source Current, ie Power in the Load. Sound familiar to anyone?

That is right. In addition to all of her other faults, it appears that Rosemary Ainslie is a plagiarist, even seeking to PATENT a circuit that has long been in the public domain.

The position of the shunt resistor is located in series with the Source, but that is the only real difference, and was done as such because all Rose's and Glen's circuits are this way.

That's right... but the circuits given in the 5-mosfet PAPERS show the same location as the diagrams in the data sheets exactly. IOW.... the diagrams in the PAPERS are false, because they didn't use the location they claim. Further, the diagram in the Quantum article is FALSE, the diagram in the IEEE submission is FALSE and the diagram in the "EIT" submission is FALSE: none of them correspond to the schematic that Steve Weir drew out from the photographs that Ainslie posted of her box.

But she has "sort of" withdrawn the NERD papers, even though anyone can still see them, without any statement of retraction (except StellaNokia's comments) ,  at Rossi's JNP, their "official publication".

She has yet to do anything about the Quantum paper lies, which have existed since 2002 and have been known by her and the public in general since 2009.

[TinselKoala]

Now.... view once again the depths of deception and prevarication that Ainslie will sink to.

A person working with a mosfet circuit who DOES NOT KNOW WHAT IS MEANT BY "DRAIN VOLTAGE" ..... but who has repeatedly shown DRAIN VOLTAGE SIGNALS from her various apparatuses..... is both willfully ignorant, and mendacious beyond belief.

Also stupid, if she thinks that anyone will buy her non-cooperative flailing about as anything other than delusional madness.

I absolutely can't say WHAT it represents.  What is that drain voltage?  I don't even understand the term.  And what circuit have you got there?  And on and on Poynty.  And WHY are you plugging this as Glen's circuit when the ONLY waveform shown is your own.  Frankly I'm done here.  If you want to talk turkey then rename this thread and IF and WHEN you show anything - EXPLAIN it better.  I absolutely WON'T engage unless I have some idea as to what you're saying. 

UNLESS, again, you have an outright admission that Glen's work was a valid replication.  In which case I most certainly WILL continue this discussion.

Rosie

HOWEVER... she has no problem at all discussing the DRAIN VOLTAGE as if she understands perfectly well what it means WHEN IT SUITS HER PURPOSES, and she has shown many diagrams and scopeshots showing a scope probe monitoring the DRAIN VOLTAGE.

However, there was still no clear evidence of what exactly was going on.  Also apparent was that while the technology was scalable - at approximately a 20 degree rise for every battery added - there was an upper limit determined by the amperage that the zener could manage.  So.  The next test was to up the ante by putting those MOSFETs in parallel.  I went for the full monty - at about 30 amps - thinking that this would still keep the battery voltage in line with the DSO's voltage tolerances.  That was when I recorded our 'first surprise' in my blog.  What was immediately apparent was there was an antiphase relationship of voltage on the source and ground rail - that spoke volumes.  When the drain voltage peaked - the source voltage was at it's lowest.  And when the drain voltage 'troughed' the source voltage was at its highest.  In effect, the returning energy trumped the output - every time - and all the way through each cycle.  Also.  The resonance - that was always restricted to a long spike and some ringing - now 'flattened out' and for a brief period gave a resonating waveform where there was clear early indications of absolute re-inforcement at each phase and stage.  But also apparent was that this resonance actually only occured when the signal at the gate defaulted to negative.  In effect - it was a negative triggering - and that's where the benefit had been hiding. 

http://www.overunity.com/10407/rosemary-ainslie-circuit-demonstration-on-saturday-march-12th-2011/49/

(Note that this post reveals once again the fact that she thinks that the drain voltage should be high when the current is flowing, but since it is not, she considers that a "surprise".)