Rosemary Ainslie Quantum Magazine Circuit COP > 17 Claims

[MarkE]

I disagree with calling the drain voltage high interval 30%.  It looks like about 70% high / 30% low.  I recommend explaining why the gate high interval of ~15% is shorter than the MOSFET low period of ~30%.

[TinselKoala]

I disagree with calling the drain voltage high interval 30%.  It looks like about 70% high / 30% low.  I recommend explaining why the gate high interval of ~15% is shorter than the MOSFET low period of ~30%.

Sorry, my fault in not being clear on the terminology. The mosfet  Drain signal is HI, at battery voltage, when the mosfet is OFF, nonconducting. I should have said that the mosfet is ON, or something like that, 30 percent of the time, supplying power to the load.

Looking at the way the drain trace develops, due to the slow response of the mosfet at 164kHz, and factoring in the ringing, leads to the estimated 30 percent ON time corresponding to the shorter Gate HI pulse of around 15 percent. The mosfet's gate capacitance takes time to fill and discharge and this means high peak gate drive currents and fast gate signal risetimes are needed at these fast frequencies, and the 555 timer clock just can't source or sink the fast risetime high current pulse needed for good clean switching of the IRFP450 mosfet.

These are just eyeball duty cycle estimates. I suppose I should break out the Link DSO to get real numbers on these.

Some versions of Ainslie's claimed schematics include a diode across the load; this will probably have a big effect on that ringing.

ETA: I haven't graphed the data but the one-hour stable temperature rise was 27.4 degrees C over ambient, and this corresponds to a power dissipation at the load of just a hair over 13 Watts. The DC input power was 16.9 Watts, and this gives an efficiency of about 77 percent, far higher than I expected. The mosfet on its heatsink was warm to the touch but not "hot". I'm sorry I didn't measure this temperature.

ETA2: This slowness of the mosfet also accounts for the seemingly anomalously high power throughput at the frequencies Glen used, around 300-500 kHz. A 20 percent duty cycle gate pulse results in the mosfet staying fully or partially ON for nearly the entire period, and I've noted this before when discussing Glen's work.

[TinselKoala]

I've put the following Note in the Description to the video:

NOTE: In the first slide I call the mosfet duty cycle "30 percent HI" at the Drain. I should have said "30 percent ON", since the Drain is of course LOW when the mosfet is ON. Sorry about the confusion, and thanks MarkE for pointing this out.

[MarkE]

Sorry, my fault in not being clear on the terminology. The mosfet  Drain signal is HI, at battery voltage, when the mosfet is OFF, nonconducting. I should have said that the mosfet is ON, or something like that, 30 percent of the time, supplying power to the load.

Looking at the way the drain trace develops, due to the slow response of the mosfet at 164kHz, and factoring in the ringing, leads to the estimated 30 percent ON time corresponding to the shorter Gate HI pulse of around 15 percent. The mosfet's gate capacitance takes time to fill and discharge and this means high peak gate drive currents and fast gate signal risetimes are needed at these fast frequencies, and the 555 timer clock just can't source or sink the fast risetime high current pulse needed for good clean switching of the IRFP450 mosfet.

These are just eyeball duty cycle estimates. I suppose I should break out the Link DSO to get real numbers on these.

Some versions of Ainslie's claimed schematics include a diode across the load; this will probably have a big effect on that ringing.

ETA: I haven't graphed the data but the one-hour stable temperature rise was 27.4 degrees C over ambient, and this corresponds to a power dissipation at the load of just a hair over 13 Watts. The DC input power was 16.9 Watts, and this gives an efficiency of about 77 percent, far higher than I expected. The mosfet on its heatsink was warm to the touch but not "hot". I'm sorry I didn't measure this temperature.

ETA2: This slowness of the mosfet also accounts for the seemingly anomalously high power throughput at the frequencies Glen used, around 300-500 kHz. A 20 percent duty cycle gate pulse results in the mosfet staying fully or partially ON for nearly the entire period, and I've noted this before when discussing Glen's work.

On the 30% versus 15% I know that you know why it occurs.  I just think that you want to explain that in video.  A 555 is not a high current gate driver.  The efficiency is relatively good because the rise and fall times are relatively good.  The rest is just the ON resistance of the MOSFET.  When you switch over to measuring Q2 oscillations, the efficiency will plummet.  A fast catch diode like a Schottky will do a lot to suppress the rising edge drain ringing.  A slow diode such as they had won't help so much.

The other thing that will be very difficult to reproduce, because there are no good measurements of it, is the extent of disruption of the 555 caused by noise in that rat's nest of a test box they built.

[TinselKoala]

As far as I can tell there are _no_ data from the Grey Box available at all.

Remember how Ainslie always says that there was no measurable discharge of the batteries in the Quantum experiment? Well, it turns out that that all depends on which version of the documentation you consult. In an early report of that experiment Ainslie published this table: