Claimed OU circuit of Rosemary Ainslie

[MileHigh]

I think that I am ready to throw in the towel myself.  I know that I said it before but I can't see this going on much longer.  When you start talking about the "right" diameter for the load resistor it starts becoming pure La-La land.  Plus the objections to Poynt's superb testing were just nuts.  It stops being fun when you start battling over nonsensical issues and you start playing the "exact replication" game.

And where does that leave the group?  Glen's DSO data is unworkable because of the negative battery power and wild variability, and Aaron gave up a long time ago and he clearly did not have the skill set to do the job anyways.  In my opinion Glen doesn't have the skill set either.  Going back a month or two there were others that stated that they would do replications but that did not materialize.  Ash's partner (can't remember his name) is not capable of generating any valid data based on his two or three contributions so far.

Ultimately it is all just a bunch of B.S. agonizing over what happens to the stored energy in the inductive component of the load resistor.  Everything seen so far indicates COP < 1.  Sorry for the non-PC trash talk but it's true.

MileHigh

[Rosemary Ainslie]

I think that I am ready to throw in the towel myself.  I know that I said it before but I can't see this going on much longer.  When you start talking about the "right" diameter for the load resistor it starts becoming pure La-La land.  Plus the objections to Poynt's superb testing were just nuts.  It stops being fun when you start battling over nonsensical issues and you start playing the "exact replication" game.

And where does that leave the group?  Glen's DSO data is unworkable because of the negative battery power and wild variability, and Aaron gave up a long time ago and he clearly did not have the skill set to do the job anyways.  In my opinion Glen doesn't have the skill set either.  Going back a month or two there were others that stated that they would do replications but that did not materialize.  Ash's partner (can't remember his name) is not capable of generating any valid data based on his two or three contributions so far.

Ultimately it is all just a bunch of B.S. agonizing over what happens to the stored energy in the inductive component of the load resistor.  Everything seen so far indicates COP < 1.  Sorry for the non-PC trash talk but it's true.

MileHigh

Sorry to hear this MH.  For the record your contributions have been much appreciated especially as they relate to waveform analysis.  But you always said your involvement was for the 'fun' it gave.  Without being fun - then why bother?  I get it.  I for one shall miss you.

By the way, and a word in for a contact of mine - I think that OC would be very glad of your skills in analysis and reverse engineering generally.  I believe he can be PM'd off this thread.  You may find some fun there.  I'm also reasonably certain that if and as this circuit analysis unfolds that you will - no doubt - reserve your rights to comment.  I get the distinct impression that you are irrepressible.

I shall, in due course be posting a small portrait of some you dancing a victory jig.  Not sure how to characterise your features from your writing.  Hope I've done you justice.  'watch this space'.  LOL 

EDIT.  Rosemary.  (I've capitulated - finally)

[Hoppy]

Folks,

See this link for a possible explanation for the coincident spikes observed in the Drain and Source. It seems to support the notion I put forward regarding inductance in the Source as the cause.

Sadly, the SPICE model for the IRFPG50 does not include the parasitic pin inductance, nor voltage dependent capacitance, and probably explains why this effect is not seen in the simulation.

Pay particular attention to "Effects of parasitic components" beginning at the end of page 9.

A very good article in general for explaining various concerns for driving MOSFETs properly. Seems to address a number of issues, some of which may also be plaguing us.

http://focus.ti.com/lit/ml/slup169/slup169.pdf

.99

I raised this modelling issue some time back. Add-ons are required to model specific mosfets more accurately. However, none of this alters the fact that the circuit is running well under unity.

Hoppy

[Hoppy]

Hoppy 
Not sure why you conclude that no replications have shown overunity?  or COP>17?

I think all test objects are to see if the efficiency barrier can exceed 1. And in some instances this has been proven.

Love your last paragraph.  LOL.  At least we can't accuse you of being open minded. 

Rosemary,

I'm certainly not open minded about OU with your circuit or any other variants presented here! I detect that others are at last seeing that this is just a big game that keeps you occupied and in a position of control. As far as I'm concerned the game is over.

Hoppy

[Harvey]

Harvey,

You say:  "We all find ourselves looking for a reason as to why 8A of current is indicated in a shunt that is isolated from the power side of the circuit by a high impedance switch while at that exact moment the other side of that switch is indicating an inverse polarity entirely prohibitive of any body diode conduction ... or any conduction through the FET for that matter."

Is it at the exact moment?? Think very carefully about this.

Hoppy

Yes. This particular scope has 4 independent A/D converters and the processor is fast enough to collate the registered values such that there is no doubt that these two are in phase with each other. The relationship has been documented on 3 different scopes: Glen's 'green screen', Glen's TDS3054C, And Poynt's scope as well. I haven't confirmed it, but I do believe Aaron has witnessed this on his scope also.

So we see 3 particular events occurring at the same time. (1) Inductive collapse and subsequent Positive Spike on the Load Resistor - MOSFET Drain Junction. (2) Increase in voltage on the B(+) Terminal - Load resistor Junction (3) NEGATIVE voltage appearing across the shunt at the shunt-MOSFET Source junction. All values referenced to B(-). The negative voltage has been logged as bottoming out around -4V at the same instant that the positive spike is peaking at around 520V. According to classical treatment of these events, the load current should be zero at this point and ready to reverse direction and the shunt should be at zero during the entire inductive collapse. The shunt should not be showing a current until after the body diode begins conducting according to classical treatment.

I have arrived at two possible classical explanations and have requested a small test to determine which of the two may be in play here. It would be nice to see others arrive at the same answers without being influenced by my POV directly. Therefore I have kept the specifics between myself and Rosemary for the moment although I have offered clues hoping to get others thinking on the matter.

Simply put, by classical approach, the negative current in the shunt should not precede the negative spike on the drain in time, especially by 180°. This is an unexpected event and begs an answer. -4V / 0.25 ohms is -16A and would be +64W at the shunt during that 100ns period. If I say anymore, I think I would give away what I think it is, and I really would like others to come to the same conclusion without me telling them what it is.