A TTL IC Based RS232 Port Expansion Interface for PC Process Control

[mscoffman]

I am going to place a do it yourself interface circuit for a PC computer
that allows one to safely interface a PC computer to control a
free engery device or for other purposes here. Please wait for post to
appear. The intent is for the user to develop their own easy to
do software driver and real time software for control of their device.

:S:MarkSCoffman

[Yucca]

I am going to place a do it yourself interface circuit for a PC computer
that allows one to safely interface a PC computer to control a
free engery device or for other purposes here. Please wait for post to
appear. The intent is for the user to develop their own easy to
do software driver and real time software for control of their device.

:S:MarkSCoffman

Hi MarkSCoffman, I look forward to seeing the development progress.

Will the unit be a serial controlled IO device, allowing the user to turn on or off many signals and maybe read some signals?

Yucca.

[mscoffman]

deleted.

[mscoffman]

PC Computer RS232 Port Expander Interface Circuit

Summary:

An RS232 I/O Port Expander Circuit is presented that allows from one to eighty input bits and from one to eighty output bits TTL transistor-transistor logic compatible signals to be generated and received over a PC Computer’s standard RS232 I/O Port. This allows a portable computer with a HLL high level language or interpreter development capability to be used as a low cost process control computer. By definition process control computers have limited external signal bandwidth and may need to be augmented externally for full utility. This allows the computer to sense and control the digital state of any external system. The minimum system consists of only ten TTL IC integrated circuits.

The RS232 port provides both; one flexible signaling cable, and protection electronics to isolate the computer electrically from the process being controlled. Even if the computer’s RS232 port is somehow damaged, the problem should not propagate into the computer’s functional circuitry. This is superior to the other means of controlling TTL level signals from the computer such as; bus interface boards, line printer parallel interfaces, USB controllers or others. This interface can easily be interfaced to an external microcomputer control processors and can be used for redundancy and debugging of an external processor or active circuits. Parts of this circuit can still be used if the user desires, by substituting a microcontroller or PAL program for IC’s number three through eight if he has those development capabilities.


Disclaimer:

It is reasonably certain that noise type problems will cause interface glitches which will require a technician’s effort to solve. These noise problems may allow the interface to be directed to *any* uncontrolled state. Further noise from the unit under control may affect the computer to stop processing causing any particular bit combination situation to happen, at any time. It is important to realize that this can and probably will happen, so that you the builder will need to be able solve these problems for themselves, You will need to guarantee the safety of the controlled process under any possible interface condition. If circuits need to be locked out of certain states, external hardware may be required to affect the lockout. This interface is for use as experimental purposes and a micro-control computer processor should eventually be substituted as replacement, as they are less sensitive to electrical noise due to their on-chip construction. With appropriate effort, all electrically noisy conditions in the interface can be eliminated.


***The First Steps***â€" Start Here

The First Steps, before anything is done or parts ordered for the interface, is to find a computer to be used as the process control computer. As it turns out the older and slower a computer is, the easier will be many aspects of this first step. Around here, working computers of this type can often be found being thrown out with the trash.  The first step is to find a computer that is reliable. This can often be tested by running the computer copying and deleting the same files for 24 hours. If the computer is still running and in control after 24 hours then it is probably reliable enough for the process control use.

Next, one has to evaluate the RS232 ports available on the computer. It would be preferable if the computer has several built in serial RS232 ports, but these are officially obsolete. You may need to get a DB9 9pin to DB25 25 pin connector adapter cables for the computer called a dongle. Your computer may only have USB ports, in which case it is suggested that you purchase a commercial USB to RS232 serial port adapter. This would be true if you want to designate a recently purchased portable computer for controlling the process. Generally one would want to start with an old slow computer, get the interface running and only then boost the speeds newer one. Any style computer with controllable RS232 port should work.

Next step is one needs to install USB software, if any, and gain port level control of the Modem Control signals on the RS232 port via the user’s choice of HLL high level language. This control may be achieved by writing directly to UART chip ports in the computer. The four hard wired Modem control signals â€" never the official RS232 Serial Data lines - are used by this interface circuit. The two sending pin are DTR data terminal ready and RTS request to send sent by the computer and DSR data set ready, CTS clear to send received by the computer and serve as input data bits to the HLL. You will have to guarantee these signals can be sent or received from your favorite HLL or interpreter unmolested by the operating system driver software. This is not so easily done under Windows OS as the ports have to be connected virtually through an OS driver. Install an “external modem” driver to do this. USB RS232 port adapters may come with documentation about other ways to gain control of the modem control signal lines. Serial data transfer is not used and is never necessary, though you may want to put the entire computer’s port UART into idle mode to keep the OS from being concerned about what is going-on on when the user is changing data on it.

Once you are able to set and clear the DTR and RTS bits from an HLL program for example displayed to a logic probe, then loop the DTR and RTS lines back to DSR and CTS and you are able to read them back in to the HLL successfully. You can now relax and have successfully completed this initial part of this interface. You may want to write a test program sending bunches of random data bits on these ports and reading them back thorough a RS232 loop back plug and comparing them to make sure no interference by the operating system is noted. Please see the Wiring List below to find the actual connecter pins for these RS232 signals. You will need an external five volt regulated power supply and ground connection to power the logic probe. You may need to pad the software port accesses with No-op’s (no-operation commands) in the HLL to keep a fast Computer from overrunning its actual computer hardware ports, signal propagation delays needed to affect reliable transfers are the user’s software responsibility. Make these easy to change variables in software program to speed up transferring software for later use on a faster computer. 


Overview Description of Expander Interface Operation

RS232 Ports are normally associated with their Asynchronous Data operations, but we use this standard port differently. The synchronous transfers we describe, are based on a user generated “clock” signal on the modem control signals RTS port line. There are four phases to the interfaces operation signaled by the user raising RTS high, then taking the RTS back low again. (one clock cycle).  So the user knows half the state information based on whether RTS is high or low. The other half the state information is provide by the state  interfaces Flip-Flop FF1 which divides the user’s RTS clock by two and outputs this information back to the user via the DSR port. The user can tell whether the interface is power is available by repeatedly sending out multiple RTS clocks and seeing if the DSR port toggles from one to zero repeatedly. The user then outputs two consecutive bits on the DTR, first the DATA bit and secondly a CTRL bit. If the CTRL bit=1 then the interface either latches the ‘N’ parallel input bits into the shift registers if the DATA bit=0. If the CTRL bit=1 and the DATA bit=1 latches the ‘N’ parallel output bits into the output latch all at once. If CTRL bit=0 then the prior DATA bit is shifted into Shift Register in the Input Chain and a DATA bit is shifted out from the Output Chain and is then made available to the CTS port where that bit can be recovered by the user and built into an internal data word built via software. The first phase is the first DATA bit, the second phase is the CTRL bit, the third phase executes the CTRL command and DATA and the fourth phase lets the user takes RTS clock back low again. The shift-registers for the input and output chains are separate and both Input and Output data shifts occur simultaneously. That makes it possible to do I and O simultaneously if desired. Obviously the user sends the CTRL=1, DATA=0 command before all the shifts happen for the ‘N’ bits being read and CTRL=1, DATA=1 command after all the shifts happened for the ‘N’ bit output to the external device under control. If the last O7 of the output chain is connected to the first D0 of the input chain, then the ‘N’ bits just sent will reappear again on the input side after the users shifts in his ‘N’ input bits. This would allow for test routines to be constructed to do a RBC read back check of the data to check for electrical noise possibly affecting the interface.  By having two sets of low level software routines with the same input parameters one can alternately have software ‘speed’ or validation ‘certainty’.


IC Circuit Wiring List for I/O Port Expander

This circuit will be built on two plastic tie-point breadboards the second one
holds the daisy chained Input and Output Shift register IC’s and parallel data
Latches and optional user interface relays or optoelectronics and driver transistors. Quality IC’s from any manufacturer are sufficient.

Device #0 - +5.0volt Regulated Power Supply, for IC’s

01 â€" POWER_VCC_5V
02 â€" GND_SystemCommon

Note; Use a +5.0 < +5.1 Volt regulated wall wart power supply, or a power
supply for USB device, or a user PC computer power supply with dummy
load on the +5VDC and +12VDC lines. One amp or greater output power capability.

Device #1 - I/O Connector-Male DB-25P RS232 Port Connector

Circuit_ref link: http://www.lammertbies.nl/comm/cable/RS-232.html#pins
Component_ref link:

01 â€" GND_SystemCommon           ; pin number - then signal name
02 â€" SERIAL_DATLoopback
03 â€" SERIAL_DATLoopback
04 -  RAW_RTS
05 -  RAW_CTS
06 -  RAW_DSR
07 - GND_SystemCommon
08 - nc.                ; no connection on this pin
09 - nc.
10 - nc.
11 - nc.
12 - nc.
13 - nc.
14 - nc.
15 - nc.
16 - nc.
17 - nc.
18 - nc.
19 - nc.
20 - RAW_DTR
21 - nc.
22 - nc.
23 - nc.
24 - nc.
25 - nc.


Device #2 -  RS232/TTL Transceiver - Maxim Semiconductor, MAX232 - 16pin DIP

Circuit_ref link: http://focus.ti.com/lit/ds/symlink/max232e.pdf
Component_ref link:

01  C1_PCAP  (+)            ; see web link for IC circuit diagram pinouts
02  C3_PCAP  (+)            ; polarized capacitors
03  C1_MCAP (-)
04  C2_PCAP  (+)
05  C2_MCAP (-)
06  C4_MCAP (-)
07 RAW_CTS
08 RAW_RTS

09 RAW_TTLNRTS
10 RAW_TTLNCTS
11 RAW_TTLNDSR
12 RAW_TTLNDTR

13 RAW_DTR
14 RAW_DSR
15  GND_SystemCommon
16  POWER_VCC_5V


Device #3 -  Econo Power-On-Reset â€" Power Monitor, DS1813 â€" Plastic TO92 Pkg.

Circuit_ref link: http://datasheets.maxim-ic.com/en/ds/DS1813.pdf
Component_ref link:

01 SYS_POWERON            ; see web link for device pin basing diagram
02 POWER_VCC_5V
03 GND_SystemCommon

Device #4 - Octal Inverter Gate - Octal Inverter & Bus Driver, 74LS240 - 20pin DIP

Circuit_ref link: http://www.classiccmp.org/rtellason/chipdata/dm74ls240.pdf
Component_ref link:

01 Loc_GND               ; connect to local on this chip - ground
02 RAW_TTLNDTR
03 CPIC
04 SYS_CMD
05 SLIC
06 RAW_TTLNRTS
07 PULSE_NCLR
08 SYS_CLK
09 RAW_TTLNDSR
10 GND_SystemCommon

11 SR_ODAT
12 SYS_NCLK
13 PULSE_CLR
14 SYS_CLK
15 NSLIC
16 SYS_NCMD
17 NCPIC
18 SYS_CMD
19 Loc_GND
20 POWER_VCC_5V         ; local to this chip VCC


Device #5 -  Dual D Negative Edge Triggered Flip-Flop, 74LS74 - 16pin DIP

Circuit_ref link: http://www.datasheetcatalog.org/datasheets/150/231700_DS.pdf
Component_ref link:


01  SYS_POWERON
02  RAW_TTLNCTS
03  SYS_NCLK
04  LOC_VCC_5V
05  MODE_DATCMD
06  RAW_TTLNCTS
07 GND_SystemCommon

08 PULSE_NENA
09 PULSE_ENA
10 SYS_POWERON
11 SYS_NCLK
12 MODE_DATCMD
13 PULSE_NCLR
14 POWER_VCC_5V


Device #6 -  Dual D Negative Edge Triggered Flip-Flop, 74LS74 - 16pin DIP

Circuit_ref link: http://www.datasheetcatalog.org/datasheets/150/231700_DS.pdf
Component_ref link:

01  SYS_POWERON
02  SYS_CMD
03  SYS_TTLNCTS
04  Loc_VCC_5V
05  SYS_DAT
06  SYS_NDAT
07 GND_SystemCommon

08 SYS_NPOWERON
09  nc.
10 Loc_VCC_5V
11 SYS_NCLK
12 Loc_VCC_5V
13 SYS_POWERON
14 POWER_VCC_5V


Device #7 -  Quad AND Gate, 74LS08 - 14pin DIP

Circuit_ref link: http://www.datasheetcatalog.org/datasheets/70/375337_DS.pdf
Component_ref link:

01 SYS_CMD
02 SYS_NDAT
03 NSLIC
04 SYS_CMD
05 SYS_DAT
06 CPOL
07 GND_SystemCommon

08 CPIC
09 SYS_CMD
10 SLIC
11 PULSE_CLR
12 SYS_NCLK
13 PULSE_ENA
14 POWER_VCC_5V


Device #8 -  Enables - Octal Inverting Bus Driver, 74AS240 - 20pin DIP

Circuit_ref link: http://www.classiccmp.org/rtellason/chipdata/dm74as244.pdf
Component_ref errata: ignore surface mount package documented in above

01 PULSE_NENA
02 NCPIC
03 RST_RSTOL
04 SYS_NCMD
05 RST_MROC
06 CPOL
07 RST_MRIC
08 Loc_GND
09 OUT_NSLIC
10 GND_SystemCommon

11 SLIC
12 ENA_NC
13 SYS_NPOWERON
14 ENA_CPOL
15 SYS_NPOWERON
16 ENA_CPOC
17 SYS_NPOWERON
18 ENA_CPIC
19 Loc_GND
20 POWER_VCC_5V

Note: 74AS part is Advanced Schotky for higher drive currents greater than a 74LS.


The Following IC’s are repeated as many times as necessary at 8 bit intervals. The Input vs Output chains may be different in length with corresponding software.

Device #9a -  Output Chain - Octal Universal Shift Register, 74LS299 - 20pin DIP

Circuit_ref link: http://www.datasheetcatalog.org/datasheets/400/373772_DS.pdf
Component_ref link:

01 Loc_VCC_5V             ; see web link for SR mode selection table
02 Loc_GND
03 Loc_GND
04 PRE_DATAOUT6
05 PRE_DATAOUT4
06 PRE_DATAOUT2
07 PRE_DATAOUT0
08 nc.
09 RST_MROC
10 GND_SystemCommon

11 SYS_DAT
12 ENA_CPOC
13 PRE_DATAOUT1
14 PRE_DATAOUT3
15 PRE_DATAOUT5
16 PRE_DATAOUT7
17 DAISY_QOUT7
18 SYS_DAT
19 Loc_VCC_5V
20 POWER_VCC_5V

Note: The above IC is duplicated as many times as the number of output bits required in eight bit sets. To use additional 74LS299’s, simply connect enable signals in parallel and join the output shift register data pin DAISY_QOUT7 to the input shift register data pin of the next higher order 74LS299. Operating software will need to take into account the length of the output bit chain.


Device #10a - Output Chain Synchronous Latches With Clear, 74LS273 â€" 20 pin Dip

Circuit_ref link: http://www.datasheetcatalog.org/datasheet/motorola/SN54LS273J.pdf
Component_ref link:

01 RST_RSTOL
02 USER_DataOut0               ; user output bit here as TTL output
03 PRE_DATAOUT0
04 PRE_DATAOUT1
05 USER_DataOut1
06 USER_DataOut2
07 PRE_DATAOUT2
08 PRE_DATAOUT3
09 USER_DataOut3
10 GND_SystemCommon

11 ENA_CPOL
12 USER_DataOut4
13 PRE_DATAOUT4
14 PRE_DATAOUT5
15 USER_DataOut5
16 USER_DataOut6
17 PRE_DATAOUT6
18 PRE_DATAOUT7
19 USER_DataOut7
20 POWER_VCC_5V

Note: The above IC is duplicated as many times as the number of output bits required in eight bit sets. To use additional 74L373’s, simply connect enable signals in parallel and join the rank's shift register output data pins to the input register data pins of the equal order 74LS273 in the Output Chain.


Device #11a -  Input Chain - Octal Universal Shift Register, 74LS299 - 20pin DIP

Circuit_ref link: http://www.datasheetcatalog.org/datasheets/400/373772_DS.pdf
Component_ref link:

01 Loc_VCC_5V
02 Loc_VCC_5V
03 Loc_VCC_5V
04 USER_DataIn6            ; user data input bit here as TTL input sig.
05 USER_DataIn4
06 USER_DataIn2
07 USER_DataIn0
08 nc.
09 RST_MRIC
10 GND_SystemCommon

11 DAISY_DI0
12 ENA_CPIC
13 USER_DataIn1
14 USER_DataIn3
15 USER_DataIn5
16 USER_DataIn7
17 SR_ODAT
18 DAISY_DI0
19 OUT_NSLIC
20 POWER_VCC_5V

Note: The above IC is duplicated as many times as the number of input bits required in eight bit sets. To use additional 74LS299’s, simply connect enable signals in parallel and join the input shift register data pin DAISY_DI0  to the output shift register data pin of the previous lower order 74LS299 with the final output pin going to the RS232 transceiver. Operating software will need to take into account the longer input bit chain. ENA_CPIC  is active high-going pulse. SYS_CMND and SYS_DATA and other signals stay stable before and after the entire CPIC signal pulse.


Passive Components Group #1 â€" Max232 IC Voltage Multiplier and Bypass Capacitors
4 Places x 2.2uf 16Vdc Tantalum polarized electrolytic capacitors

1 C1_PCAP
2 C1_MCAP

3 C2_PCAP
4 C2-MCAP

5 C3_PCAP
6 Loc_GND

7 Loc_GND
8 C4_MCAP


Passive Components Group #2 â€" Max232 IC Converter Data Deglitch Capacitors
2 places 100pf, 2 places 47pf

1 RAW_DTR
2 Loc_GND

3 RAW_RTS
4 Loc_GND

5  RAW_TTLNDTR
6  Loc_GND

7  RAW_TTLNRTS
8  Loc_GND

Passive Components Group #3 â€" DS1813 Line Delay Capacitor
1 places .1uf 25wvdc capacitor

1 SYS_POWERON
2 Loc_GND

Passive Components Group #4 â€" Resistors 74ALS240 Inverter Enables pull-up
4 places x 330Ohm ¼ watt axial lead or SIP inline pgk, carbon composite resistors

1 R1 - Loc_VCC_5V
2 ENA_CPIC

3 R2 - Loc_VCC_5v
4 ENA_CPOC

5 R3 - Loc_VCC_5V
6 ENA_CPOL

7 R3- Loc_VCC_5V
8 ENA_NC


[End of Wire List section]

Parts List for I/O Port Expander

---

1 x  Maxim Semiconductor MAX232, 16pin plastic DIP (.10 inch pins, dual inline pkg.)
1 x Dallas Semiconductor DS1813 Power on Reset, 3pin To92 plastic package
2 x 74LS74 Dual D Flip-Flops, 14pin plastic DIP
1 x 74LS240 Octal Inverting Bus Driver, 20pin DIP
1 x 74LS08 Quad AND gates, 14pin DIP
1 x 74AS240 Octal Inverting Bus Driver, 20pin DIP

---

2 x 74LS299 Universal Shift Register, 20pin DIP
1 x 74LS273 Octal D Type Latch, 20pin DIP

Note: I/O Shift Chains; As many as Bit ‘N’/8 rounded up IC’s as required by ext. device.

---

1 x DB25P male pin connector for RS232, clam shell housing
1 x 5.0 - 5.1 volt regulated power supply, 1 ampere or more output current capability
1 x 24AWG set of plastic insulated solid hookup wire
2 x white plastic tie point bread-board with power and ground busses, five IC capacity

---

20 x .1uf 25Vdc working voltage VCC to GND IC all IC’s bypass capacitors.
1 x 100uf 16VDC working voltage VCC to GND bulk power supply bypass capacitor.
4 x 2.2uf 15Vdc working voltage tantalum electrolytic capacitors for MAX232 dc-filter
2 x 100pf 50Vdc RF bypass capacitors for active RS232 input lines of MAX232, noise
2 x 47pf 50Vdc RF bypass capacitors for active RS232 TTL outputs of MAX232, noise
4 x 330ohm ¼ watt resistors, axial or SIP single inline package, for 74AS240 pull-ups.

---

1 x 1.2Kohm ¼ watt resistor, for base of following 2N2222
1 x 2N2222 NPN T092 transistor, beta current gain of  approximately 100
1 x 1N914 diode (freewheeling)
1 x Relay 5volt 600ohm coil, 1 amp SPST reed relay
1 x 4N10 optoisolator, led, 1MHz bandwidth, transistor output

Note: These last components are not part of interface but allows one
to design a typical isolated output switch for connection to it   

[End of Parts List]

Data Selector Table Documentation I/O Port Expander

Pulse Flip-Flop(enable strobe)    CMD/Data Bit(sent last)      Latched Data Bit(sent first)

             1                                        0                                X      aa
             1                                        1                                0      bb
             1                                        1                                1      cc


Actions for Above:

      aa â€" send Latched Data bit FF-3 to Shift Register then shifts right.
      bb â€" load inputs from Input chain into shift register. Subsequently shifted out to CTS   
      cc -  latch the contents of  Shift Register to Output chain Latch â€" do not shift


Sequence Table Documentation for I/O Port Expander

The following table is the sequence of steps that is occurring within the interface;

*    ~  - indicates an IC propagation delay occurs (short electronic delay)
*    U - indicates a user system software computer delay occurs (long user delay)

The Numbered steps are interface sequences and the Alphabetic steps are the User requires sequence.  Note: A CPU Processor interrupts can extend software delays without affecting final results adversely.

User read the DSR port to make sure it is equal to zero…If not, user sends RTS from high to low and back â€" then DSR is read and should have toggled to a One. User can use this repeatable DSR toggling sequence to detect that interface is properly connected, powered up and ready to control the external unit.

0   [Instantiate a Zero into the Data/Command State Flip-Flop FF1, see above]

   *   U (delay type)

1A   User Places Serial DATA bit to DTR   - (DATA OUT)

*   U

2B   User Places ONE to RTS   - (CLK HI)

*    ~

3   Self toggles a One to Data/Command Flip-Flop â€" FF1

*    ~

4   DTR Input Data latches into Data Storage Flip-Flop â€" FF3

*   U

5C   User Places COMMAND to DTR   - (CMD OUT)

*   U

6D   User Places ZERO to RTS   - (CLK LO)

   *   ~

7   A ONE from STATE Flip-Flop â€" FF1 is latched into PULSE Flip-Flop â€" FF2

*   ~

8   Pulse Enables go out from Decoders â€" The active enable goes low

   *   ~

9   Shift Register; Shift Right, Input or Output Latches is activated

   *   U

10E   User Places ONE to RTS   - (CLK HI)

   *    ~

11   Data/Command Flip-Flop â€" FF1 Toggles to Zero 

   *    ~

12   Pulse Flip-Flop - FF2 Clears to Zero

   *    ~

13   All Decoder Enable Pulses Terminates â€" enable signals all go high

   *   U

14F   User Places ZERO to RTS   (CLK LO)

   *   U

15G   [Input Optional] User Reads serial DATA bit in from CTS

   *   U

16   [Input Option] Users begins next bit sequence again at step 2 above.

17-note; When User has output all ‘N’ bits of the interface â€" the LATCH command is sent to the 74LS273 register so all bits are updated as simultaneously as possible (within nanoseconds). The controlled device never sees data bits rippling through the shift register, plus all bits are updated simultaneously. Note that power on resets sets all output bits to Zero = Off â€" Controlled device should be stable or stop running with ‘all control bits equal Zero’ in the event the interface power is somehow lost. This reset state is what defines the interface to have ‘positive logic’.

17   User therefore sends CMD=1, DATA=1 to interface to Strobe Shift Register data byte to 74LS273 Latch using the above sequences to update all the output data bits simultaneously which is sent on to the unit under control.

[End of Sequence Documentation section]

{End-of-Text}

[mscoffman]

Hi MarkSCoffman, I look forward to seeing the development progress.

Will the unit be a serial controlled IO device, allowing the user to turn on or off many signals and maybe read some signals?

Yucca.

Thank you, Yucca. I've already used this interface (a similar) circuit to
control five different projects in a variety of ways. It actually avoids using
the RS232 serial data data because serial data that takes a more
complex LSI chip, plus frequency determining element - a crystal. This
design is as simple as possible. One actually could use the serial
data on this port in some other way, like talking to a microcontroller's
serial port. You can get a feel for what makes this interface go
by looking at the sequence table documentation near the end of
the next post.

The goals were;

a) to make this as simple as possible out of available inexpensive TTL IC chips.
b) make it indefinitely expandable to 80 bits input and 80 bits output
without additional TTL buffers.
c) have PC software do most of the work, modern PC's are very fast
d) protect the PC computer's internals through the use of RS232 interface electronics
d) have a definite digital state on Power-on
e) to have all the output bits updated simultaneously to avoid race conditions
f) to support I/O interfaces that do not transfer more than a microscopic
amount of energy in either direction into or-out of the "core circuit"

It can definitely be used to interact with a microcontroller;
just connect one input line and one output line to one of the
microcontroller's I/O ports. If the host wants the microcontroller
to do an internal sequence it can raise the output port for a
time until the microcontroller sees it.

Some of the things I've done with it; You can read raw EPROM's.
Download a microcontrol program into dual ported Ram on one
side of the ram while the micro waits patiently for the release
of its reset signal on the other. Exchange bidirectional parameters
the same way while the micro is running.

For overunity projects it can remove tedious control of switches,
do energy monitoring, data acquisition and archiving. The PC host
method lets the user program in wide-words using his favorite
high level language and use the computer's real time clock routines
for tasking control. This allows for easy use of advanced control
algorithms. So this interface is all about doing as much as possible
with all around as little as possible.

Once the user has experimented with the best way to control things
he can write a microcontroller program that takes over control
tasks completely while still using his PC for manual control, monitoring,
performance data acquisition etc.

---

All;

The previous post contains the listing of this interfaces wire list.
A (nearly) identical version of the document in MS-Word 2002
Editor (sorry about the proprietary tools) is attached to the post.
The best bet may be to open the attachment in the text editor,
select all text, reduce the font size to eight points and  then
print on a laser printer. Sorry about the length, but I wanted to give
enough documentation so it can be seen to work after parts are
purchased. These are handy DIP IC's to have around in any case.


:S:MarkSCoffman