another small breakthrough on our NERD technology.

[picowatt]

To all,

In consideration of a replication, I have been studying the two "papers" to which our focus is to be directed.

In the two "papers", even though the schematics appear to transpose the quad and single MOSFET connections, we can assume that in either circuit, regardless of whether the "quad" is Q1 or Q2, when the function generator output is positive, at least one MOSFET will be turned on, or at least partially so.

Referring to the first of the two papers presented (Experimental Evidence of a Breach...), FIG 3 depicts the conditions for "Test 1".  If I am reading this LeCroy scope shot correctly, it appears that during the period when the function generator output is positive, the gate drive is approx. +12.5 volts.  During this same time perod, the voltage across Rshunt appears to indicate little if any current flow (i.e., little if any Vdrop across Rshunt).

How can this be?  If we assume that irregardless of which schematic is referenced, at least one MOSFET is connected in such a way that it would turn on fully with this level of positive voltage applied to the gate, there should be current flow indicated by the voltage at Rshunt.

In FIG 5, which references "Test 2", it appears that the gate voltage during the same positive FG period is approx. +5 volts, and, just as one would expect, the voltage across Rshunt indicates that approx. 2 amps are flowing.  Consulting the data sheet for the IRFPG50, the indicated two amps is (depending on device temp) in fair agreement with this level of gate drive.

Am I reading these levels correctly on the scope shots?  If so, in the FIG 3 scope shot referencing "Test 1", it would appear that the MOSFET that should turn on at the indicated gate drive level is either disconnected from the circuit or has gone "open circuit" (a fairly atypical failure mode as DS shorts are more common)

If anyone has an alternate explanation or if I am reading the LeCroy shots incorrectly, please explain.

PW

   

[TinselKoala]

Hmmm... for reference I have attached the relevant figures from the paper below.

It sure looks to me like picowatt is right. In Figure 5, in fact, there does appear to be _less_ positive gate drive voltage than in Figure 3. With a positive going gate drive pulse of 10-12 volts as indicated in Fig 3 there should have been a mosfet turning on, and we'd see this in both the CVR trace and in the common drain trace (missing on these screens).

This paper claims to use the FIRST crossover circuit, though... the one that would heavily load the single Q1 mosfet during a positive gate pulse. And as I believe I have shown, with a 60 or 72 volt battery pack and the 11.11 ohm load,  this mosfet would likely fail rapidly because its absolute maximum drain current and power dissipation levels (not well heatsunk) would be exceeded.

So perhaps picowatt is right: we are looking at a trace from a system with a blown mosfet. Any other explanations?

(Isn't it interesting that the oscillations are happening during the LOW or off phase of the gate drive signal ?)

In the text of the paper we find:

A. Test 1 Setup
The schematic in Fig. 1 refers with the following settings: 6
batteries x 12 volts each were applied in series. The offset of
the function generator was set to its extreme negative limit
resulting in an entire restriction of current flow during the ON
phase of the duty cycle. The duty cycle is also set to the limit
of the function generator’s shortest ON time within each
switching period of 2.7 minutes. The waveforms produced by
this setup are shown in Fig. 3 and Fig. 4.

But the gate drive signal shown in Figure 3 clearly shows a positive-going signal. I think if the LeCroy's channel trace invert is selected a symbol appears in the channel setting box, but I can't really recall.


It also appears that these are not live waveforms, they are stored and displayed from memory (the M at top left, the memory menu on the right side of the screen). With filenames like "bloc1068" and "bloc1029" it's easy to see how one might select the wrong waveform from memory and not display the intended one. But it's more likely that they have a blown mosfet, open from the heat, rather than shorted from overvoltage.

[TinselKoala]

There is something else funny about those traces. Note in Figure 5 the scope is computing the integral of the CVR trace.... and its mean, max and min are all positive. It's very weird to want to see this integral... but the fact that it IS computed and the values that are given mean that the net voltage drop across the CVR is POSITIVE, even accounting for the swings above and below zero during the oscillations. Presumably the scope is integrating across one full cycle. Please correct me if I'm wrong here, but I don't think it matters to the conclusion.
And of course the battery trace is always positive even during its wildest (illusory) swings.
Yet the scope's math trace, simply doing a point by point multiplication of these two traces, comes up with negative mean, max and min values. There is only one way this could happen, and it's not "reverse current flow". I think that would have shown up as a negative value on the integral of the CVR trace.

[picowatt]

TK,

I had not considered that CH3 imght be inverted in one of the scope shots.  I do not believe that to be the case, as both views show the oscillation that occurs when the comon gate amplifier is biased on by the negative voltage from the FG. 

SO, that leaves two possibilities, an internal D or S bond wire or the die was fused open in one or more MOSFET's (depends on which circuit is correct, just Q1 if as in the first paper), or one or more MOSFETS was removed/disconnected from the circuit during the test (again, Q1 if the first paper schematic is followed).

Assuming Q1 is fully turned on and RDSon equivalent to something close to 2R, Rload = 11R1, and Vbatt=60vots, Q1 would dissipate ca. 40 watts via about 4.5 amps flowing through the circuit.   Thermal stress (over temp) more often causes a short between the drain and source.  A severe overcurrent can fuse the bond wires or blow the package apart, but the IRFPG50 has a max Id of 6.1 amps, usually indicating the bond wires/wafer can handle at least that much current (as long as max wattage/temp is not exceeded).  With thermal stress, a D/S short is a more common failure mode.

In any of your 830's that you "blew" from overtemp, what was the failure mode?  D/S open or shorted?

PW


 

[Rosemary Ainslie]

To all,

In consideration of a replication, I have been studying the two "papers" to which our focus is to be directed.

In the two "papers", even though the schematics appear to transpose the quad and single MOSFET connections, we can assume that in either circuit, regardless of whether the "quad" is Q1 or Q2, when the function generator output is positive, at least one MOSFET will be turned on, or at least partially so.

Referring to the first of the two papers presented (Experimental Evidence of a Breach...), FIG 3 depicts the conditions for "Test 1".  If I am reading this LeCroy scope shot correctly, it appears that during the period when the function generator output is positive, the gate drive is approx. +12.5 volts.  During this same time perod, the voltage across Rshunt appears to indicate little if any current flow (i.e., little if any Vdrop across Rshunt).

How can this be?  If we assume that irregardless of which schematic is referenced, at least one MOSFET is connected in such a way that it would turn on fully with this level of positive voltage applied to the gate, there should be current flow indicated by the voltage at Rshunt.

In FIG 5, which references "Test 2", it appears that the gate voltage during the same positive FG period is approx. +5 volts, and, just as one would expect, the voltage across Rshunt indicates that approx. 2 amps are flowing.  Consulting the data sheet for the IRFPG50, the indicated two amps is (depending on device temp) in fair agreement with this level of gate drive.

Am I reading these levels correctly on the scope shots?  If so, in the FIG 3 scope shot referencing "Test 1", it would appear that the MOSFET that should turn on at the indicated gate drive level is either disconnected from the circuit or has gone "open circuit" (a fairly atypical failure mode as DS shorts are more common)

If anyone has an alternate explanation or if I am reading the LeCroy shots incorrectly, please explain.

PW

Thank you very much.  We've finally got an appropriate observation.  INDEED that's what we've been pointing to in that first test of that first part of that two part paper.

The current flow from the supply is blocked through adjustments to the off set that there is no current flow at all during the 'on' period of the duty cycle.  Then during the 'off' period when the battery is indeed prevented from discharging any energy we have evidence of an oscillation that can persist for the full duration that the negative signal is applied to the gate of Q1. 

The intention of Paper 2 is to resolve those paths.

Test 2, 3 and 4 were performed to show the exploitable potential in that configuration proposed to be due to the explanation in the second part of that paper.

Regards,
Rosemary
added