Testing the TK Tar Baby

[TinselKoala]

Here I post another page from Ainslie's blog. It makes some remarkable statements.

http://newlightondarkenergy.blogspot.com/2012/01/230-some-examples-of-that-misdirection.html

I know this is English. But it makes claims that are manifestly untrue in the English that I speak. Are the mosfets in the Q2 array not in parallel? Is there something magic about them that makes a mosfet or mosfets able to carry 5 amps at a resistance of 2 ohms and not get warm in the slightest? And are not the "resistors" forming the "shunt" in parallel? And if this is a typo meant to say "transistors" are not the mosfets of Q2 in parallel? And what magic keeps them from being subject to the same problems that all paralleled mosfet arrays are subject to?

I dunno. Sometimes I think somebody isn't really being completely straightforward with the facts. Other times I think that somebody just doesn't know what she's talking about and is making stupid, but ultimately innocent, mistakes. And then still other times I know that she's deliberately lying to string this out and garner as much attention, positive or negative, as possible.

The links referred to in the blog post are : the first two to the same IEEE paper on the danger to mosfets in parallel arrays from parasitic oscillations, or some such irrelevant garbage, the third is to a .pdf on the same topic from Advanced Power Technology, a major manufacturer of power mosfets, written by their chief engineer. And the fourth is to the famous "Hate Blog" which I love.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1645505
http://www.sz-sunny.com/APT/application%20note/apt0202.pdf
http://rosemaryainslie-publicblog.blogspot.com/   which has changed, but the new link is on the page referred to by this link.

A fine example of misdirection indeed. Note that she insults half the people on the planet in her last sentence. "LOL". But after all... half the people on the planet ARE below average, aren't they.

[TinselKoala]

TK,

How you label the components doesn't change the fact that this circuit has two modes of operation:

1. The circuit is in a DC mode and there is NO OSCILLATION.
2. The circuit is in a AC mode and there IS OSCILLATION.

So for the circuit you posted in the above post, the bias at red is + and - to the black.
This makes your circuit go into DC mode where your Q1 will be fully on conducting current.
Your Q2 will be off with NO oscillation.

So I want you to test the bias current on your circuit when your Q1 is ON and there is NO OSCILLATION in your circuit.

GL.

OK, that is clear, thank you. I agree that the "labelling" doesn't make a difference in how the components behave -- as long as there is only One of Each. When Q2 becomes a stack of 4 then it matters on which side it is because the 4 can clearly carry more current without overheating.
But if we are to understand one another we should agree on the labelling at least.

I will remove all but one of my Q2s, and I will use 24 volts for the battery, which should give me some time before the single Q1 mosfet heats too much, and a 13 volt input from the power supply, polarity as you have it, 50R in series, and I'll measure the current with the inline DMM which should be good, right? It has an inline resistance of 1.8 ohms which should be added to the total gate circuit resistance.
Since there are no oscillations the simple DC measurement should be adequate, I hope.

Give me an hour or so.

[TinselKoala]

OK... to be perfectly clear... this is the setup that GL is requesting that I examine. Right? Last chance for corrections !!
I've put in Tar Baby's component values so that the currents expected can be calculated and compared to GL's results. Don't forget we have different Rdss mosfets and slightly different other values, and my inline DMM milliammeter will have 1.8 Ohms of its own internal resistance.

[Groundloop]

OK... to be perfectly clear... this is the setup that GL is requesting that I examine. Right? Last chance for corrections !!
I've put in Tar Baby's component values so that the currents expected can be calculated and compared to GL's results. Don't forget we have different Rdss mosfets and slightly different other values, and my inline DMM milliammeter will have 1.8 Ohms of its own internal resistance.

TK,

Sorry for the delay, a storm is passing and my mains went out.

Yes, that is what I want you to test.

And when you are done testing and found the bias current then you can do a theoretical
analyze and see if the current you got agrees with your theory.

GL.

[MileHigh]

Groundloop:

That looks excellent.  It looks like you have explained the very high current when the gate voltage on Q2 is high.  (Referencing your schematic.)

Now it seems very obvious.  I, and perhaps others, was fooled by my preconception that there should be no current flow.  I didn't even think about the diode in Q1.

Current from the +13-volt bias source flows through the 50-ohm resistor and then leaks through the diode in Q1 and then flows through Q2 and then back to the +13-volt bias voltage source.

This is a separate current loop independent of the main current loop driven by the +24-volt source.  This "extra" current loop causes a kind of negative 'feedback' on the main current loop and reduces the current flow in that loop very slightly.

So that was fun.  It shows the investigative process in action, and you figured out the mystery.

MileHigh