Kapanadze Cousin - DALLY FREE ENERGY

[itsu]

to itsu

Try old 1N5408 for DSRD diode in Nano-Pulser !! Use HV capacitor for Nano-Pulser 1-2n 1.5-2kV DC, minimum.

Сергей Ð'.

i see this is yet another variation on the Dally diagram, it now uses a PNP and a NPN transistor for driving the MOSFET :-(

I will stick to my mosfet driver (max4420) for the time being.

Thanks for the suggestion for the 1N5408 diode and HV cap.

Regards Itsu

[Сергей В.]

to verpies

Yes, you are right !!. Sch is good for PMOS but we need NMOS. I've corrected. Thanks !!

[Сергей В.]

to Itsu

Yes you have right about clocking NMOS. I've mentioned earlier about using high speed driver. You can conect gate directly to driver output. Then best solution is to put MOSFET as possible as you can near the output pin. When you mount you can put driver on another small board on MOSFET radiator. I think it can "fly" on MOSFET gate. On this way you will solve usual problem with parasitic oscillations on MOSFET gate.


ps. Still not news from Dally !! We all still expecting oscillograms of Dally Generator. One friend tell me he used ferrite ring from TV antenna premplifier. If you can find will be nice to try one of this rings. I haven't information about parameters of these ferrite rings!!

If you need ultra High Speed driving MOSFETs you should make something like this driver. Last picture. Use Gigahertz input trasistor for clocking push-pull MOSFETs!!

[d3x0r]

Re the TL949 schematic...

The only +5 V is from the clock chip to the various transistors...

So probably... which would like trim the rising edge of the wave to the first PNP (it will be open and conducting with voltage from the diode to the collector until the base is at a certain voltage, which will turn itself off... normally these aren't even conducting because the wave is low. 

I'm only getting barely over a volt on the gates of the E13009's... before the resistor I have a nice 5V rise... and I would think that during the time the pnp is not conducting, that 5V should develop on both sides of that resistor...

Or is there suppose to be a pullup on the collector of the pnp, maybe a large resistor to power?

[verpies]

Re the TL949 schematic...
The only +5 V is from the clock chip to the various transistors...

Where do you see +5V on this schematic?

I'm only getting barely over a volt on the gates of the E13009's...

E13009s don't have gates.
BJTs are not voltage driven like MOSFETs, they are more current driven.

Take a look at the attached schematic.
This schematic is almost the same as yours. It is laid out differently and the transistors Q1, Q4, that are inside of the TL494 Integrated Circuit, are brought out and depicted as uncircled transistor symbols.

Note that the collectors of Q1, Q4 are connected to Vcc (+12V in this case) and the main job of these transistors is to pull up points I and G to Vcc, through the diodes D1 and D2.  Their minor job is to pull up the bases of Q2 and Q5 to Vcc.

Now, consider what happens when Q1 or Q4 stops conducting: Without Q2, Q5 and R2, R5 there would be nothing that would pull down the points I and G to ground. 

That would be bad because points I and G would float and any accumulated charge appearing at those points would stay there for a long time without being discharged to ground - this would result in very slow fall times at points I and G (especially if Q3 and Q6 were transistors of the MOSFET type, that has capacitive gates).

Fortunately, when Q1 and Q4 are not conducting, Q2 and Q5 come to the rescue by actively pulling down points I and G to ground.  In other words - they complement each other (namely: Q2 complements Q1 and Q5 complements Q4).

This happens because R2 and R5 pull down the respective bases of Q2 and Q5 (points F and H) more negative than their emitters, when Q1 and Q4 are not conducting and not pulling those bases up. Note that emitters of Q2 and Q5 (points I and G) can be more positive than their respective bases, when Q1 and Q4 are not conducting, only when there is some remaining positive charge at points I and G.

The purpose of the diodes D2 and D1 is to prevent points I and G from pulling up points H and F, respectively.
Due to D1 and D2, only Q1 and Q4 can pull up the bases of Q2 and Q5 (points F and H).

In summary, the transistors Q2 and Q5 act as active pull-downs, because the internal TL494 transistors Q1 and Q4 are only capable of pulling up the points I and G to Vcc (e.g.: +12V).

The active pull-downs allow the bases of Q3 and Q6 to be quickly jerked up and down (Vcc and Gnd), however because of the way BJTs work, the voltage between the base and emitter of Q3 and Q6 rarely rises above 0.7V.  Read this for an explanation - why.

Does that help at all?

P.S.
It is much more interesting to measure the voltage between the emitters and collectors of the Q3 and Q6 transistors, while these transistors are conducting.  If this voltage does not fall to zero then it means that Q3 and Q6 are underdriven and are not conducting fully.