Kapanadze Cousin - DALLY FREE ENERGY

[verpies]

It is reverse biased. During reverse it conducts from ground to drain as ground is at higher potential level due to the negative spike presented at the drain.

That's the problem, a positive (2*V_CC) pulse should be present at the drain which is caused by the conduction of the other transistor.

[Jeg]

That's the problem, a positive (2*V_CC) pulse should be present at the drain which is caused by the other transistor conducting.

The current reversing happens only momentarily during transition. After that, and when the gate signal is being applied everything goes normal again. When one drain gives positive spike after closing, the same time on the other drain a negative spike is presented. This negative spike goes to ground through the reverse diode, and the same time current flows from ground (anode) to drain, until the gate signal to be applied.

[itsu]

I can see reverse current conduction through point 2 (the MOSFET).

Could I bother you for another scopeshot with 8μs gate pulse, but with more than 1 cycle but less than 2 cycles visible,  ...and both gate signals visible ?

Also, I'd appreciate if the current probe was flipped around, so the current looks like it is increasing when the gate signal is high.

8us gate signal, not sure what you mean by: "but with more than 1 cycle but less than 2 cycles visible"
both gate signals shown

Current probe flipped around.

Itsu

[verpies]

The current reversing happens only momentarily during transition.

That is the problem. During the so called, inductive "flyback" the current does not reverse in an inductor.

When one drain gives positive spike after closing, the same time on the other drain a negative spike is presented.

I don't know what you mean by the "drain gives a positive spike" because the voltage spike originates in an inductor - not in the Drain.
The Drain "gives" only 0V (ground) when the MOSFET turns ON ...otherwise it is floating except for the body diode.

When the Drain is pulled down to 0V by the MOSFET, the other half of the primary pulls the drain of the other MOSFET, up to 2*V_CC.

See the altered diagram from here.
If you go to that article - it is the lower left one.

[verpies]

8us gate signal, ...both gate signals shown
Current probe flipped around.

Thanks.  Are TVS diodes installed ?

not sure what you mean by: "but with more than 1 cycle but less than 2 cycles visible"

For analysis of periodic waveform it is advantageous to view the entire cycle on the scope's screen, but viewing 2 cycles is too much, because it worsens the horizontal resolution.

So viewing 1 cycle <= on screen < 2 cycles, is the best.