Eldarion and Bruce's build of Bob's Energy Converter

[eldarion]

Well, I finally got a 10:1 probe, and also got direct data capture over the GPIB bus working!

So, here is an updated scope shot of the driver waveforms on channel 1 (bottom) with a 10:1 probe, and the switched primary coil end waveform on the top (channel 2) with a 1:1 probe:
http://www.falconir.com/pics/withten_one_probe_on_channel_1.jpg

As you can see, the gate drive is not really as bad as you might have thought based on the first scope shot...

Eldarion

[eldarion]

Well, here is a quick update:
The old hand-wired board with the MAX627s on it was severely distorting and altering the pulse sequence--I disconnected it and scoped across the FPGA's TTL outputs, and a perfect waveform was observed.  I guess there was just too much interference being picked up by the horribly long wire lengths.

So, I will stop this unproductive line of testing and concentrate fully on building the new driver board.  I got several of the UCC27322 SMD chips installed, along with their bypass capacitors, and some other through-hole support components.  Unfortunately I am still waiting on the main 40-pin right-angle header (in the UPS system somewhere), so I will not be able to install any more parts until I get that installed.  This is so that I can test my work as I go, rather than potentially having to troubleshoot an entire "finished" board at once.  I do believe we should see some positive results once this board is finished; having the 4-channel digital 'scope is really aiding design and troubleshooting here!

Eldarion

[Bob Boyce]

At the docs office on broadband WiFi so I can finally get caught up on all of the threads with pictures.

@eldarion

Glad to hear you figured out where the problem was. Breadboarding is good for really low frequency testing of parts but as you seen it can get a bit "hairy" as speed is increased.

I have my own problems I'm dealing with. I have the need... the need for speed ;-) My 20 MIPS is topping out pretty low when running all 8 channels, and still too low when cut back to 4 channels. I'm not finished with trying coding tricks.

Bob

[eldarion]

Hi Bob,

If you like I can send you one of my unstuffed driver circuit boards and the control software--once I have checked everything out on mine, of course!   The FPGA can easily go to 500KHz+ on the primary frequency, and while driving 6+ channels.  Whether the driver board will keep up without distortion or timing glitches is the only question...

Just let me know the pulsing sequence I should create for 6 or 8 channels, and I will update the control software!

Eldarion

[Bob Boyce]

Hi Bob,

If you like I can send you one of my unstuffed driver circuit boards and the control software--once I have checked everything out on mine, of course!   The FPGA can easily go to 500KHz+ on the primary frequency, and while driving 6+ channels.  Whether the driver board will keep up without distortion or timing glitches is the only question...

Just let me know the pulsing sequence I should create for 6 or 8 channels, and I will update the control software!

Eldarion

I would love to give the FPGA approach a try for sure. The pulse sequence is like that which was pictured earlier, will attach it here. In order to maintain exacting timing relationships, I am producing pulses for all 3 channels, but directing the missing pulses to unused port pins. I am driving the B channel set and A channel set with a slight adjustable phase offset from one another. If I were to time them exactly together, I could reduce complexity a bit and increase speed. I may end up doing that, but for now I like having the option of phase shift between sets. The other 2 channels are for PMW controlling the control windings, so they are driven different. I will probably change the channel arrangement around and use a dedicated PWM channel pair for this function. As it is now, I am generating my 2 PWM channel signals totally via code instead of using the internal PWM channels where I can set and forget until it needs to be changed. I am reading my ADCs twice per code loop currently to get high priority to changes, that can also be reduced.

Bob

Forgot to mention. My pulse sequence is 12 pulses long, then repeats, makes for some pretty simple code at this point.