Ultracaps tested for excess energy

[PaulLowrance]

Paul:

Correct me if I am wrong, but your line of investigation is that you charge the cap slowly and measure the capacitance and voltage you know approximately how much energy is in the cap.  Then if you discharge the cap quickly or in some other fashion and can deduce that the capacitance is larger, the you have shown OU.

Hi,

It's difficult to say with any acceptable accuracy how much energy went into the bcap while charging, and how much energy went out during discharge because the measurements were not logged fast enough. That why we need a data logger.

What I am saying is that if the capacitance changes and the amount of charge on the capacitor remains the same, then the voltage on the cap will go down all by itself without any discharging.  You will measure a larger capacitance with delta-Q/delta-V, but the voltage on the cap at that instant in time will have dropped.  You will not get more out of the cap than you put into it by changing the discharge rates.

Not if there's a dynamic voltage source within the ultracap, which is why it *might* be excess energy.

With respect to the apparent increased measurement of the capacitance, I don't think that is related to the temperature of the cap going up.  The effective series resistance of the cap is very low, so my gut feel is that the temperature of the cap will rise marginally, but this will not affect the measured capacitance.

I agree the bcap temperature does not change much. I've documented the bcap temperature, although this data was not posted. This is only external temp, not internal. What might be happening is high temperatures occurring on small micro structures.

Although there is correlation between the temperature & capacitance.

I can offer up a theory.  I am not an expert in supercaps, I only read up on them a tiny bit and I was also skimming.  Since the separation between the "plates" is so small (something like 20-40 microns) and the dielectric layer is some sort of flexible layering of molecules, I am going to assume that it is "spongy" based on your results.  Whatever the dielectric layer is made up of, for sure it is some sort of flexible ultra-thin membrane.

As the capacitor charges up to higher and higher voltages, the attraction between the "plates" of the capacitor gets higher and higher because of the opposite charges attracting.  So as the capacitor voltage gets higher and higher there is an ever increasing attraction force and this squeezes the dielectric layer and makes it a tiny bit thinner.  Suppose for the sake of argument that the dielectric layer separation goes from 40 microns thick to 35 microns thick when the capacitor is charged to its maximum voltage.

This decrease in the thickness of the dielectric layer results in the supercap having a higher measured capacitance.  That's my theory for your consideration.  I would not be surprised with enough Google searching that you would find the true explanation and I may not be right, but at least on track.

Note also that this is what your data is showing.  The higher the voltage the higher the measured capacitance.  My theory is based on your data and my limited knowledge about supercaps and good overall knowledge of electronics.

For those that don't understand why decreasing the thickness of the dielectric layer increases the capacitance, Wikipedia awaits you.

MileHigh

Yes, it does show that, but to make such an assessment with the data I've posted so far is beyond reason. That effect appears to be minor effect. For instance,  the first measurement of the day during the ultracap *discharge* measurements was 595F and the ultracap with a discharge from 695mV to 685mV @ 188.4mA @ 66.6°F.  Trust me, 595F is nothing compared to the measured capacitance during mid to final measurements, at least according to the data.

As stated, there is the effect of the ultracap voltage changing as it settles down after being used. This voltage change was almost non existent in the charging measurements because the ultracap had time to rest between measurements. Although the discharge measurements consisted of non-stop discharging, and there was a noticeable after effect of the ultracap voltage settling down, which is expected. Even when I consider the ultracaps final voltage after it settled down, it still amounts to far beyond 600F, but I don't like using this data to determine that. We need to do data logging to know for certain. 


Paul

[PaulLowrance]

Hey Paul,

A few more thoughts for your consideration.  I will assume that your printer port/ADC chip data logging setup can plot your acquired data.  I will also assume that your current source is a true constant current source, especially considering the low voltages that you are working with.

If the capacitance does not change as you do a slow charge then the voltage vs. time plot should look like a straight line (you can set it to 45 degrees for example).

If the capacitance does increase then the voltage vs. time plot should look like some sort of curved line with the slope decreasing.

If you get this plot than you can test your thermal theory to see if it explains the phenomenon.

It's a bit of a pain but if you put the setup near your sink and somehow arranged for a continuous slow flow of tap water with the cap sitting in the water, then you will remove any excess heat from the cap as the test runs.  Let's assume that your tap water will be a constant temperature.

So with the cap in a flowing "water jacket" you rerun the test.  You know that the cap temp will pretty much remain constant and you can check out what the voltage vs. time plot looks like to see if the capacitance is changing or not.

Finally I want to mention that Poynt gave a link about the issues involved for measuring the values of capacitors.  The effective series resistance does come into play because the higher your current the more energy lost in charging or discharging.  I think that the paper stated that the "safe" way to measure a supercap using the 37% method was to do a very slow discharge over hours using a relatively high resistor value.  It was a very informative paper and you might want to find the link if you haven't read it.

MileHigh

That's not necessary because I'll be logging both voltage & current. The current does not even have to be constant. I'll use a current source for the charge, but the discharge current will vary some, especially as it approaches 0mV.

Paul

[powercat]

Paul, Will you be posting any new results today.
cat

[PaulLowrance]

Paul, Will you be posting any new results today.
cat

Hopefully. The data logger circuit is right here next to this computer where it's being debugged. Some good news is that it appears to be working now. That is, the ADC along with the PC connection w/ software. 

One issue, although needs further study, is that this ADC0809 does not appear to like a low Vref+ source. It simply would not work! When Vref+ was bumped up to 0.809V, it was happy. Not sure how low it can be. Maybe there's a datasheet comment  on this.

To do list:
1. Adjust Vref+ to the lowest allowable voltage.
2. Calibrate.
3. Move & connect all of the ultracap stuff here.
4. Write the MSVC++ code to do the datalogging. Might take up to an hour.
5. I might use the secure computer that's never connected to any network because I don't want to take the chance of the data being hacked.  The secure computer is Vista, while the computer that I'm using right now is XP. So there might be some Vista issues.

Well, maybe it's fine to leave Vref+ at ~ 0.8 volts. I mean, regardless it will have the same range, which is 0 to 255. My goal is to see if the ultracap is *obviously* > cop 1. If it's like cop 1.01, then someone else can spend the extra time require for such precision. I'm looking for something that's considerably higher.

It's lunch time now! 

Regards,
Paul

[powercat]

Thanks for the update and good luck with Vista ,I would stick with XP myself (reliability)
Great work.
cat