@GL: I sure will. Probably have to wait until after dark, though !

ETA: I see one source of my confusion. In the schematics I have been using, a Positive signal from the FG's Positive output goes to the Gate of Q1, not Q2. Most of the discussion in the thread to this point has been assuming this schematic, I think. But in your schematic the positive signal goes to the gate of your Q2. Hmm.

No matter, all I have to do is flip the designations in my head when I look at your diagrams, I think. But it might be helpful if we could standardise things.

The Ainslie diagram with the designations I have been using is below.  A positive gate signal emitted by the FG positive terminal goes to Q1 gate and Q2 sources. I think in your diagram a positive signal goes to Q2 gate and Q1 source.

I am getting very confused. This looks like the "negative bias mode" but with the Q2 fully on instead of oscillating.

Ah.. I think this now. To properly simulate the DC "negative bias mode" that I've been exploring lately.. that makes oscillations and uses a strict negative bias current....  the "shunt" resistor should be connected to the negative side of the battery on one side and to the POSITIVE bias voltage input, not the negative one, on the other side. This puts the bias supply and the main battery in series. The way you've got it the bias supply and the main battery are "fighting" each other's voltage. I think. So if you just moved that shunt lead up to the other bias wire that would do it. And that is also why the bias supply must be floating wrt the other main supply.

Here's the negative DC supply schematic that I've been using.

I'm no longer sure just what we are discussing now. If we can agree on the mosfet designations and the bias polarity hook ups, I'll try do repeat the tests you've done and suggested. I'll use the same voltages that you use if I can arrange it with my batteries and supplies.

Your diagram is clear. I'll have to see what it will take to do it that way with Tar Baby. But any explanation about mosfet designations and so on will be very helpful to me.

Quote from: TinselKoala on May 13, 2012, 06:00:03 PM
@GL: I sure will. Probably have to wait until after dark, though !

ETA: I see one source of my confusion. In the schematics I have been using, a Positive signal from the FG's Positive output goes to the Gate of Q1, not Q2. Most of the discussion in the thread to this point has been assuming this schematic, I think. But in your schematic the positive signal goes to the gate of your Q2. Hmm.

No matter, all I have to do is flip the designations in my head when I look at your diagrams, I think. But it might be helpful if we could standardise things.

The Ainslie diagram with the designations I have been using is below.  A positive gate signal emitted by the FG positive terminal goes to Q1 gate and Q2 sources. I think in your diagram a positive signal goes to Q2 gate and Q1 source.

I am getting very confused. This looks like the "negative bias mode" but with the Q2 fully on instead of oscillating.

TK,

It is not that complicated. If you put a positive bias voltage into my 50 Ohm bias resistor then:

1. My Q1 will shut off and no current could flow through that transistor.
2. You can now remove the Q1 but leave the internal Q1 diode in the analyze drawing.
3. The Q2 transistor will turn fully on conducting current.
4. So you can remove Q2 and use a 1,6 Ohm resistor in the analyze drawing.
5. The internal diode of Q2 in this DC mode will not have any effect so you can remove that also from your analyze drawing.
6. The circuit is in pure DC mode so you can use Ohms law to do the analyze.

I did use 24 Volt on my input. With Q2 fully on I got 1,74 Ampere flowing. The bias voltage was 13,74VDC and I did
measure 0,09 Ampere bias current. For 0,09 Ampere bias current to flow the bias load must be 91 Ohm.
Now, looking at the input points for the 24 volt we see 10 Ohm + 1,6 Ohm + 025 Ohm = 11,85 Ohm. This gives
a theoretical current of 2 Ampere. In real life I got 1,74 Ampere.

Now look at the bias part. The theoretical analyze says: 50 Ohm + Resistance of Q1 internal diode + RdsOn.
The Q1 internal diode has a voltage drop of 1,8 Volt so the theoretical resistance should be approx. 20 Ohm.
So we get 50 + 20 + 1,6 = 71,6 Ohm. This is far from what the measurement says. The measurement says
that the bias resistance must be close to 91 Ohm. But what RdsOn is the bias circuit seeing? If we use the
0,09 Ampere through the RdsOn then we can find the voltage drop over the RdsOn as seen from the bias.
You find the voltage over the 50 Ohm and voltage over the 20 Ohm (Q1 diode resistance) and then I found
that the RdsOn that the bias is seeing is not 1,6 Ohm but 30,93 Ohm. Now if I add up I got 90,93 Ohm as
total resistance for the bias. And that is in agreement with the measured result.

Now the paradox, how can the RdsOn be 1,6 Ohm for the 24 volt path, but 30,93 Ohm for the bias path?

ADDED: I'm discussing the bias input current in the DC mode with a positive bias input when the circuit is NOT oscillating.

GL.

"ADDED: I'm discussing the bias input current in the DC mode with a positive bias input when the circuit is NOT oscillating."

OK.... but in the schematic I've been using, the one that supposedly has been "approved", a positive bias input that doesn't make the circuit oscillate goes to the gate of Q1, not Q2.

Take a look at the diagram below. I've removed the bias source altogether, and labelled the "input" points according to the colors of the Ainslie FG (and both my F43 and WaveTek FGs ) output leads: red for the inner conductor ("+") and black for the outer conductor ("--"). Note the mosfet designations... my Q2 and presumably Ainslie's is on the left side.

So, in your tests that you are describing, what is the polarity of the voltage that you are applying to the "red" and "black" points, using this schematic's mosfet designations?

Quote from: TinselKoala on May 13, 2012, 08:11:14 PM
"ADDED: I'm discussing the bias input current in the DC mode with a positive bias input when the circuit is NOT oscillating."

OK.... but in the schematic I've been using, the one that supposedly has been "approved", a positive bias input that doesn't make the circuit oscillate goes to the gate of Q1, not Q2.

Take a look at the diagram below. I've removed the bias source altogether, and labelled the "input" points according to the colors of the Ainslie FG (and both my F43 and WaveTek FGs ) output leads: red for the inner conductor ("+") and black for the outer conductor ("--"). Note the mosfet designations... my Q2 and presumably Ainslie's is on the left side.

So, in your tests that you are describing, what is the polarity of the voltage that you are applying to the "red" and "black" points, using this schematic's mosfet designations?

TK,

How you label the components doesn't change the fact that this circuit has two modes of operation:

1. The circuit is in a DC mode and there is NO OSCILLATION.
2. The circuit is in a AC mode and there IS OSCILLATION.

So for the circuit you posted in the above post, the bias at red is + and - to the black.
This makes your circuit go into DC mode where your Q1 will be fully on conducting current.
Your Q2 will be off with NO oscillation.

So I want you to test the bias current on your circuit when your Q1 is ON and there is NO OSCILLATION in your circuit.

GL.