The gathering together continues. Here is SCRN0150. This is what I believe a "proper" run is supposed to look like.

Envelope period is just under 700 us... call it 690 us, for an envelope frequency of about 1450 Hz, and the duty cycle looks to be about 120/700 or about 17 percent ON.

Gate drive: About +5 HI and some negative with oscs LO, indicating the negative offset of the FG and showing that there is bias current flowing when it is LO.

CVR trace: Shows good strong current during the Gate HI intervals, about 550 mV drop or 550 mV/0.25 Ohm = a nice healthy 2.2 Amps flowing. Interesting. The battery is a 4-stack of just over 49 volts.

The math trace shows the instantaneous power during the Gate HI periods quite well.

So here it is clear that the mosfets are behaving pretty much as expected although the current in the Gate HI phase still seems a little low to me.

Let's see.... if the mosfet is fully on its Rdss 2.0, CVR 0.25, load 11.11, battery and other wires 2... total circuit resistance should be around 16 Ohms. I=V/R, so 49.5/16 = 3.1 A, But we are only doing 2.2 A, so the TCR must be higher. Perhaps the mosfet isn't quite turning fully on yet with the only 5 volts or so gate drive. For 2.2 amps the TCR must be V/I = 49.5/2.2 == about 22 Ohms. About 13 - 14 of this is in the load and wiring so the mosfet must have an internal resistance of about 8 or 9 ohms. Let's use 8. So the power dissipated in the entire circuit during the Gate HI intervals is (2.2 x 2.2) x 22 == about 106 Watts instantaneous power. So the power dissipated in the mosfet will be (2.2x2.2)x8 == about 39 Watts and in the load (2.2 x 2.2)x11.11 or about 54 Watts, and in the shunt (2.2x2.2)x0.25 == about 1.2 Watt, so that is 94.2 Watts out of the 106 accounted for. The rest will be in the battery and the leads.

Looking at the math trace now.... again during the Gate HI periods... I measure with my calipers about 22 VxV. Since one of those Vs is actually a scaled A value, and since the current value is 4 times the voltage value on the shunt, we do VxVx4 to get to the actual instantaneous power during the Gate HI periods, and I make that about 88 Watts. In rough agreement with the other measurements and calculations.
But of course this is only the instantaneous power during the ON time and this mosfet is OFF when the Gate signal is LO. So applying the duty cycle of about 0.17 we get an AVERAGE power dissipation of the total circuit of about 15 Watts, of which about 9.2 Watts will be in the load, and about 6.6 Watts in the mosfet AVERAGE power dissipation.  And this is JUST the contribution of the  Gate HI "ON" portion of the signal.
This ignores the contribution from the negative bias oscillations during the Gate LO part of the period, of course, so the true power delivered to the load will be greater. But the Q1 mosfet will definitely feel warm to the touch at about 7 Watts average.
And... if the _period_ is lengthened, even if the duty cycle stays the same, or if the battery pack is increased to 72 volts.... or both... or if the gate signal is made more positive during the HI portions... the Q1 mosfet will be stressed.

Since we clearly have power being delivered to the load and dissipating in the mosfet during the NON OSCILLATION PORTION OF THE SIGNAL..... where is the magic? There are no oscillations to fight the battery current and keep it from discharging, so it MUST BE DISCHARGING even under the terms of the "thesis". The only way to defeat this OBVIOUS DISCHARGE DURING THE NON_OSCILLATIONS is to somehow postulate that the battery IS being recharged DURING THE OSCILLATIONS, to offset the evident discharge during the non-oscillations.

So..... if there IS NO DISCHARGE PERIOD, that is, no Gate HI period to discharge the batteries, the CHARGING EFFECT OF THE OSCILLATIONS should over charge the batteries and cause the voltage to rise, not stay constant. And I mean RISE, because .... the oscillations must produce a charging effect at least as great as the DISCHARGING effect, corrected for duty cycle, if the battery is to remain at a constant charge. When the discharge is removed by using only the negative bias mode...... the oscillations should overcharge the battery. I mean, I didn't tell them we weren't going to be sneaking an ON portion into the cycle... did you? SO how do they know not to overcharge the battery?

http://www.youtube.com/watch?v=4EjCHuqdKUs

Quote from: Rosemary Ainslie on May 15, 2012, 10:32:26 PM
Poynty

I still don't get it.  Are you describing what would be happening under ideal circumstances when the switch is 'on'?   Because otherwise I fail to see the relevance.  Please let me know.

Regards,
Rosie

Rosemary,

I think we've been trying to uncover the operating conditions for the "positive bias mode", in which Q1 is actively ON, and while only Q2's diode is involved, as per the drawing. We are looking at this bias condition and the resulting circuit currents.

You can see that this mode is somewhat more complex in terms of the current paths, where there is a secondary (bias) loop within the main current loop. A fine example of KCL at play.

Quote from: poynt99 on May 15, 2012, 08:00:57 PM
GL,

I would encourage you to measure your actual VGS, as I have a hard time believing that it could be 7.5V.

All my sims show no more than about 4V max when Q2 is installed.

.99,

Yes I did and I also indicated that on the drawing in the post "Here is what I did measure".

It was +7 Volt.

GL.

Rosemary:

Our esteemed readers can look at your message to me and decide for themselves.  I am only doing this because there was nothing confidential or personal in the message:

Quote

(Quoting MileHigh:) Take the example of the bias supply current loop.  Let's say that the real Q2 Rds is 3.5 ohms.   What the +13-volt bias supply 'sees' for the Q2 MOSFET drain-to-source voltage drop is ((3.5 ohms x 0.09 amps) + (3.5 ohms x 1.78 amps)).  The second term is the counter-EMF generated by the main current of 1.78 amps flowing through the same MOSFET.

You may want to look again at this post of yours MilesOffTheMark.  What is r x I?  Don't you mean I^2R?  And then correct it before its TOO LATE.

Rosie Pose

Rosemary, you are in attack mode right now and you are talking like an idiot.  You talk like an idiot in your message to me shown above.

Repeat, you are not qualified to make any comments about what I posted, inane or otherwise.  Shame on you for being in the gutter with your attack postings about my investigation.  It's simply disgusting and everybody that is reading you is squirming looking at you making a spectacle of yourself yet again.

I won't discuss this matter any further.  Get out of jackass mode.

MileHigh

Quote from: poynt99 on May 15, 2012, 09:40:06 PM
Actually, the MOSFET current INCREASES when the bias (Q2) is added. The load current DECREASES when the bias (Q2) is added.

The reason for the difference between Q2 present and Q2 absent, is because the RDsON state of Q1 changes in each case. In other words, the bias condition of Q1 changes.
It is more than simply "resistance". There are two voltage sources bucking each other in series, and one must consider that as well. See my updated drawing below. I had to correct the measurements because I forgot to remove the 2 Ohms of wire resistance between the batteries and the circuit in my last simulation (I used the NERD circuit with all the wire inductance and resistance).


The bias current is calculated as follows:
- Determine the voltage at point "V": 1.84A x 11 Ohms = 20.24V across Rload.
- Now subtract from 24V to get 3.76V.
- Now subtract from the 12V bias supply to get 8.24V and
- Divide by the total resistance of 50 + 4.8 (for the diode, or use 11.3V vs. 12V) = 150mA
(there is probably an easier/quicker way, but the above is a simple explanation)
In the case shown below, 13 Ohms, which is just about Rload + RdsON. But I hope you understand that it is a little more complicated than that, as you saw above for your other related question.
No problem. As a point of interest, note the indicated VGS voltage and the ON resistance for Q1?

.99,

>>>The reason for the difference between Q2 present and Q2 absent, is because the RDsON state of Q1 changes in each >>>case. In other words, the bias condition of Q1 changes.

I agree that the bias situation is different in the two cases but it does NOT change that fact that the MOSFET
is biased fully ON at each case and the GS voltage is +12 Volt in one case and +7 Volt in the other.

The RdsOn starts at very high Ohm when there is no positive voltage on the Gate (ref. to S). The RdsOn then
go down in Ohm when we increase the G voltage. But at some point the RdsOn will NOT go down anymore
because we have reached the saturation of the MOSFET and the RdsOn have reached the data sheet RdsOn of 1.6 Ohm.
It will not go lower than that. So in my case the linear region of the MOSFET current control ends at approx. 6 Volt.
ALL voltages on the G above that voltage will put the MOSFET into saturation.

Your simulation is not showing what I'm measuring. I did measure the GS voltage and found it to be +7 Volt
with both MOSFET transistors IN the circuit, and +12 Volt when I pulled the other MOSFET.

What is the RdsOn for the 24 Volt main current of 1,74 Ampere?
24 Volt / 1,74 Amp = 13,79 Ohm -10 Ohm = 3,79 Ohm - 0,25 Ohm = 3,54 Ohm = RdsOn

What is the RdsOn for the 12 Volt bias current of 0,09 Ampere?
12 Volt / 0,09 Amp = 133,3 Ohm - 50 Ohm = 83,3 Ohm
The internal diode has a voltage drop of 1,8 Volt. Gives, 1,8 Volt / 0,09 Amp = 20 Ohm.
So, 83,3 Ohm - 20 Ohm = 63,3 Ohm = RdsOn.

How can the RdsOn be different for the two cases at the SAME TIME?

GL.