Active power from parallel resonance. Test circuit and research.

[Jim36]

Pomo, yes it's a circuit for OU (I hope).

Verpies,

1 Joule is a lot in electronics.
But why do you think that the parallel LC circuit will give up more energy then it took to energize it?
Please compare the forward voltage drop of a Triac vs. a MOSFET, while keeping in mind that the power lost inside the Triac is equal to the product of the current flowing through it and its voltage drop.

Yes I know 1 joule is a large amount for electronics, this is a power device utilising mains rated power electronics to switch on and off close to 0V on each half cycle. Actually I calculate it at 1.44Joule though there will be parasitic losses not accounted for like you said across the Triac (I will calculate this). And also losses within the inductor / capacitor parallel circuit though I will size the wire to be able to handle large current and the inductor will be from a transformer primary, capacitor will be a motor run type.

This is what I want to run by you. Why does a parallel LC circuit (tuned to resonance) draw any current on start up when an AC voltage is applied? I haven't practically tested it and probably missing something as it does seem too simple. My thoughts are the capacitor and inductor will require equal current at the same time but of opposite direction as they are 180 degrees out of phase, therefore the current cycles between them selves and does not draw from the mains?

SmOky2, thanks for editing the picture

Cheers

[sm0ky2]

SmOky2, thanks for editing the picture

Cheers

no problem.  If you go back and edit your original post, removing the (large) photo, it will resize the thread page and make it easier for people to view.


the problem I see here, is going to be a difference in Impedance between the tank circuit and the other parts of the circuit.
namely T2, and the common lead back to source.

[sm0ky2]

this creates a reactance, to the source.
which will alter the measurement of power input if not properly accounted for.

[verpies]

Why does a parallel LC circuit (tuned to resonance) draw any current on start up when an AC voltage is applied?

Because the phase offset between the external AC voltage and the internal AC voltage across the parallel LC circuit is not 0º.
This phase offset occurs not only during startup but also any time that phase of the external AC voltage is changed.

Most importantly, the current draw happens anytime the voltage across the capacitor is smaller than the instantaneous voltage of the the external AC voltage.

[Jim36]

Smoky2, I can't edit the original post only my later replies for some reason? I'm new to the forum so having a few teething issues! If you could point me in the right direction

Verpies, Thanks for your explanation. You say that a phase offset between the source voltage and voltage across the circuit
cause an initial current draw to charge the parallel circuit which would be exactly the same amount of current as a capacitor only circuit
or inductor only circuit? What phase angle is this initial current with the source voltage? Have you seen this under test
circumstance yourself? I can't find any information on this phenomenon so would appreciate any links to help explain.

Thanks