Graham Gunderson's Energy conference presentation Most impressive and mysterious

[verpies]

What kind of leakage takes place if the MOSFETS are constantly on?
In order to pass energy through a parasitic Miller capacitance don't we have to have AC present?

No, any change in the voltage appearing between the gate and drain is enough.  Even one pulse.  Many cycles of AC are not required.

Also, if the source's potential is free to vary (as in a source follower) then the energy can flow from the gate to the source circuit, too.

In this circuit the MOSFETS are on for 20 uS  (50 k cps) and then are briefly shut off for 5 to 1000 nS (I don't know the exact timing).  Wouldn't this very narrow duty factor have a tendency to reduce the kinds of losses you are addressing?

Yes, the duration of the period when dv/dt is greater than zero, will affect the gate leakage proportionally.  In my calculation above, I accounted for a 0.5% duty factor and a pulse having dv/dt = 600V/1us.

The amount of the MOSFET's gate leakage depends on the overall circuit configuration and should be measured empirically for best accuracy.

[Spokane1]

Dear All,

Here is my first shot at the Schematic for the Synchronous Diode Sub Assembly. Comments and suggestions are welcomed.

Spokane1

[k4zep]

Dear All,

Here is my first shot at the Schematic for the Synchronous Diode Sub Assembly. Comments and suggestions are welcomed.

Spokane1

What a prodigious amount of work there Spok1.  Is there possibly a small problem with the rectifier diode for the negative -5 volt regulators?
Possibly a CT on the transformer in that portion of circuit connected to common.

Ben K4ZEP

[Spokane1]

Dear K4zep

You are absolutely right, I need to make some adjustments there.

Also Graham likes to use two large tantalum capacitors with each MOSFET driver, which are not shown in this drawing version.

I'm not to sure about the wired logic that controls the start-up and shut down of the power supply switching transformer, I believe that the intent is to have any of the regulator/storage circuits start the power switching when a low voltage condition is detected. I would also think that an over voltage condition would shut down the power supply MOSFET as well, thus two Zener's per isolation monitor.

I'm not really sure where the main power switching element is. That little transistor looking thing next to the Driver chip looks to small to run six low power regulators. It could be on the back of the circuit board along with all the needed storage capacitor's.

I'm not a switch-mode power supply designer. Graham's intent was to make a very low energy power supply to provide a great deal of isolation at the highest efficiency that would run the Synchronous Diode circuit. He has spent years designing and building these kinds of circuits, so I believe that what we are looking at is the best there is using DigiKey components.

Spokane1

[TinselKoala]

Thanks Spokane1 for the diagram, I can appreciate how much work that is. That's all well and good, but I'm having trouble believing that the circuit you've drawn out could provide enough current for the driver chips to switch into the Gate capacitances of the mosfets at 50 kHz. Where does the input power come from for this circuit? Is it coming from the breadboard?