Claimed OU circuit of Rosemary Ainslie

[henieck]

If the DRAIN has a 3.7% duty cycle, IS IT or IS IT NOT conducting current from a power source for 3.7% of the time per pulse?

It really is a simple yes or no question.

- what is a duty cycle? To me normally it indicates signal like from 555 timer where you have voltage and current in phase. What are you referring as duty cycle while talking about the Drain? Is it about voltage or current?

[TinselKoala]

OK then, if Aaron thinks the way he does, how does he explain my video?

Am I faking something?
When anyone with a scope and a few components can do EXACTLY the same thing?

Where's the error here? Can't you SEE that when the drain signal is high, the mosfet is OFF?

How is that light lighting up when the drain signal is low, if  Aaron and Rosemary are right?

And, once again, "if" I am right, what does that do to the calculations in her paper?

Are you accusing me of faking this video? When ANYONE with a scope , the knowledge to use it, and a few components can do it for themselves?

And has Joit reported his light-bulb results yet?

[ramset]

TK
I might get thrown off the buss [hopefully not under]
Chet

[TinselKoala]

- what is a duty cycle? To me normally it indicates signal like from 555 timer where you have voltage and current in phase. What are you referring as duty cycle while talking about the Drain? Is it about voltage or current?

http://en.wikipedia.org/wiki/Duty_cycle

Henieck, a duty cycle is a parameter of a pulse train that gives the proportion of HIGH signal to LOW signal. A pulse train, that is a set of rectangular pulses like that we have been dealing with. Normally duty cycles are considered in percentages. So a perfect square wave would have a duty cycle of 50 percent.

Now, in a situation where the baseline is at zero volts and the peaks are at 10 volts like the 555 timer gives, you consider the time the signal is LOW (at baseline) compared to the time the signal is HIGH. One cycle, or many, it doesn't matter as long as you use complete cycles.

But the Ainslie paper is talking about current being conducted by the load, and she appears to believe (edit) (along with Joit and some others) that the load is conducting when the DRAIN of the mosfet is high. The peaks in Joit's trace, and in the last trace shown in my #7 video, those peaks are at battery voltage, and the low parts are somewhat (not much) lower. This signal must be read on AC coupling as the signal is much smaller than the DC offset. So, it's easy to see how the mistake was made. She appears to think that since the "duty cycle" at the drain is HIGH only 3.7 percent of the time, that the mosfet is ON at that time and conducting current through the load. But as I have shown, and as others agree, this is backwards.

Sure, the DRAIN duty cycle is 3.7 percent high, no argument there. That means the transistor is OFF for 3.7 percent of the time. That's where the argument is.

But that's not the duty cycle of interest---it's the LOAD's duty cycle we need to know for the calculations, and it's only the assumed shortness of that cycle that makes this OU claim possible. If the cycle AT THE LOAD is long, there's no mystery about the load heating up to 50 degrees over ambient.

And that's what I believe has happened.

So fine, if someone wants to call the drain signal a 3.7 percent duty cycle, that's OK with me, as long as everyone knows the MOSFET is OFF at that time. Not ON.

[ramset]

TK
I must say you are a saint [not a religious one]
I sincerely appreciate your tolerance and sharing /teaching nature
And you got skills
Chet