I am not sure if I want to be involved in any way TK. Often people want me involved so they can use my name, like saying its been University tested as they were standing on the front lawn of University at the time.
To be honest I am not technically qualified to do any evaluation, and my friends and engineers who are I rather not risk introducing them to her.
However there is one really smart guy I know in South Africa who might just be interested in testing. He is a very bright electrical engineer and knows many of the tricks used by over unity claimants (South Africa is full of them). I will send him an email and see if he is interested.
Mark

Quote from: markdansie on June 05, 2013, 08:33:25 AM
I am not sure if I want to be involved in any way TK. Often people want me involved so they can use my name, like saying its been University tested as they were standing on the front lawn of University at the time.
To be honest I am not technically qualified to do any evaluation, and my friends and engineers who are I rather not risk introducing them to her.
However there is one really smart guy I know in South Africa who might just be interested in testing. He is a very bright electrical engineer and knows many of the tricks used by over unity claimants (South Africa is full of them). I will send him an email and see if he is interested.
Mark

Mark, when you contact your friend in SA, please send him the links to Ainslie's papers, but most definitely send him the Figure 3 scopeshot and the schematic I posted right above, so that he can judge for himself whether or not the Figure 3 shot is possible to produce with that schematic and a properly functioning Q1 mosfet. The mosfet is getting +12 volts, roughly, to its gate during the 16 second ON portion out of the 160 second total period, yet is passing absolutely no current during this time. And it's on the "heatsink" shown in the photo below! I've also included the data sheet for the IRFPG50 mosfet that she uses, for your friend's convenience.
This woman really needs reining in. I was hoping you would help to do it, but I can certainly understand why you would not want to have further contact with her. Anyone who is critical of her winds up being flamed, insulted, and even threatened legally and yes, even physically by her, however empty those threats might be.
The heatsink that Ainslie was using on the Q1 mosfet at the time the Fig3 scopeshot was made:
(This photo was taken by her before the Q2 mosfets on their large heatsinks were added to the circuit. The March 2011 Demo Video shows that this heatsink was still in use then, and the Figure 3 scopeshot was made after the Q2s were added (obviously) but before the March 2011 Demo. This is the heatsink she used for the trial described in Figure 3, no doubt about it.)

TK or anyone else who has not been banned could they please reply to Rosemary's open letter on my behalf and let them know i can not reply because I am banned.
Kind Regards

Well, I am probably "banned" too, since my most recent comments seem to be vanishing. Isn't that great? They flame and libel, take stuff out of context, make false claims without any support, and don't even allow replies to direct communications by the parties concerned.

Mark E. seems to be still allowed to post, but I don't know if he reads here.

TK,

Just a couple points.

Regarding Q1 and FIG3 in the first paper (not the COP=17 paper, the "other" first paper...), we cannot be certain that Q1 was "blown", it may have been disconnected or not connected as per the schematic.

In FIG3, during the portion of the FG cycle wherein the FG output is a positive voltage, the FG output trace indicates that +12 volts is being applied to the gate of Q1.  As most will agree, +12volts applied to the gate of Q1 should turn Q1 fully on, yet, during that same portion of the cycle, the CSR trace indicates that there is no current flowing at that time.

In FIG5, a capture from the month prior, during that same portion of the FG cycle, +6volts is indicated as being applied to the gate of Q1 and, as expected, the CSR trace indicates that Q1 is turned on and passing current.

The only possible explanations for the lack of indicated current flow in FIG3 during the positive portion of the FG cycle are that Q1 was either defective, disconnected, or not connected as per the schematic during the tests related to FIG3.


With all the confusion regarding how the Q2 MOSFET's were connected (as in which is the real schematic?) and all the clipleads used to connect the MOSFET's, it is possible that a lead or pair of leads was/were disconnected or reversed as they attempted to make the circuit more "COP=17 like".

Either way, with Q1 "blown", disconnected, or not connected as per the schematic, her data that relies on the tests related to FIG3 is invalid and should have been retracted or corrected (as discussed at great length some time ago).
   

Also, when she refers to her oscillations persisting even though the battery is "disconnected", please realize that I believe what she actually means is that she sees no path for DC or AC currents during the portion of the FG cycle wherein the FG output is a negative voltage.  She does not actually mean that she "unhooks" the battery.

Recall the struggle to get her to understand that a FG can sink or source current, and how Q2 is turned partially on when the FG applies a negative voltage to the source terminal of Q2.  To this day, from her continued claims, she still does not understand how Q2 is biased on into a linear operating region as a common gate amplifier with DC bias current flowing thru Q2 and the FG, and AC currents flowing thru the intrinsic capacitances of all the Q1/Q2 MOSFET's.  Instead she makes wild claims that her oscillations somehow defy, or cannot be explained by, everyday electronic theory and practice.

Just wanted to clarify,

PW