Yes, thanks PW, I believe that I generally do include the "missing or disconnected" options whenever I say things like "not according to the schematic claimed".  And unlike some others, I don't make up new definitions for terms like "disconnected" or "isolated" or "floating".

However, if you consider the 16-second ON periods, the 73+ volts supplied, and the tiny joke of a "heatsink" used on that mosfet you will also have to agree that the mosfet can easily fail due to heat stress. In fact a friend who understands heat transfer requirements made an educated approximation and gives it less than a minute of life on that heatsink if the thing is kept ON for the entire time instead of being allowed to rest. Turning the FG "duty cycle" knob approximately 1/3 of a turn, and leaving it there for less than one period at the frequency shown, so that the mosfet stays fully ON for over a minute (35 or 40 percent duty cycle and a 160 second period) will almost certainly result in an open Q1 from overheating, right away, and with the FG settings exactly as shown in the scopeshot, the heat will still build up in the mosfet and it will fail, it will just take a bit longer. And the only way the circuit can produce high heat in the load is to have the Q1 mosfet on for substantial amounts of time. It is important to realize also that Ainslie used the tiny heatsink for that shot, and the much larger heatsink now visible on the photos at PESN is a new addition. Why? Recall that she has claimed several times in several insulting posts that the mosfet does not heat up. Of course, failed mosfets do not heat up, and in fact cool off rapidly when they are no longer conducting. And further, recall that she has _never again_ shown a case where the entire six batteries were used in "high heat" mode. The previous demo video even disconnected one of the 5 to leave only four, and the present photos show only _three_ batteries in use to make the high heat, and the Q1 is on a much larger heatsink!

I _know_ the shot was made with something wrong, and thus the conclusions and claims based on it are wrong. I _strongly believe and contend_ that the thing that was "wrong" is that the mosfet failed from heat stress, rather than being disconnected or missing entirely or miswired. I "trust" that the schematic we have been given is, finally, the correct one used, although I do recall the month long deception that Ainslie engaged upon in March and April of 2011. I believe that there exists a fair body of circumstantial evidence that supports this belief.  One such bit of evidence can be seen in the sequential series of scopeshots taken just before Fig3, which are available for view (no thanks to Ainslie) at
http://seani.justemail.net/rosemary_ainslie/
The SCRN numbers are the filenames assigned by the scope and the scope display includes the date and time of the screenshot. I think you can actually see this, or another, mosfet failing.

And I _know_ that there is an easy way to resolve the situation: Have Ainslie repeat the scopeshot under full scrutiny re schematic, connections, mosfet integrity and so forth. It would take you or me less time to do that demonstration than it took us to write our last two posts, and you know it. If... that is.... it were possible to do it at all.

And even further: Why do you think she added the four Q2 mosfets in the first place? She originally was working with the single mosfet with the same other parts. But she kept blowing mosfets! Somebody told her to add four more in parallel on heatsinks to handle the current! And when she did, she accidentally miswired them! Therefore, she still has the same overheating problem in the single transistor as before !
It is a comedy of errors, when you have all the information and start assembling it in chronological order.


And even furthermore.... if she only really HAD used the schematic in the version of Paper2 posted on Rossi's JNP right now.... with the four parallel mosfets on the right, gates connected to the Red or " + " FG output lead  .... she wouldn't have had the overheating problem in the first place, since she would have 4 transistors playing the role of Q1 in the circuit instead of just one, and the circuit will oscillate just fine on a single transistor in the Q2 role. But she's repudiated this schematic as being the wrong one, and of course it is not the one she actually did use. (So why am I able to take this screenshot today, then? Because it is still up, in the only "official publication" of Ainslie's manuscripts.)

(Even these schematics are wrong, though, because in the March 2011 demo and in every photo that exists of her work with the required detail, it can be seen that the Black FG lead (wrongly marked " - " on the schematic) is actually connected at the common circuit ground, that is, _on the other side_ of the current viewing resistor R_shunt. Bypassing it.)

Quote from: TinselKoala on June 05, 2013, 03:12:10 PM
And even further: Why do you think she added the four Q2 mosfets in the first place? She originally was working with the single mosfet with the same other parts. But she kept blowing mosfets! Somebody told her to add four more in parallel on heatsinks to handle the current! And when she did, she accidentally miswired them! Therefore, she still has the same overheating problem in the single transistor as before !
It is a comedy of errors, when you have all the information and start assembling it in chronological order.

TK,

I agree with all that you say, particularly when considering Q1 having to dissipate up to 60 watts or so when turned on, and some of the ugly waveforms that were seen just prior to Q1's on current changing to zero.

I also agree that a Q1 failure is a definite possibility, but to be clear, based only on the scope shot of FIG3, we can only know for certain that Q1 is not connected or functioning as per the schematic.  If, for example, they reversed the Q1 gate and source lead, they would have made a 5 MOSFET Q2 array and the waveforms would as well look like those in FIG3.

As for the whole sordid tale, and the reason they attempted to parallel aditional FET's (and did so incorrectly leading them to accidentally discover their common gate oscillator), all is very likely just as you suspect.

Note that in FIG5, where Q1 is functioning correctly, it looks like Vbatt is closer to 50 volts.


PW

QuoteIf, for example, they reversed the Q1 gate and source lead, they would have made a 5 MOSFET Q2 array and the waveforms would as well look like those in FIG3.

Ah... but then "they" would not have been able to make the high heat in the load. The point still stands: the shot is invalid and so are the claims and conclusions proceeding from it.
Only the "wrong" schematic above is capable of making the high load heat at 72+ volts input without stressing the mosfets.

But just as I demonstrate in my Cheese Power videos, in the absence of coherent explanations to the contrary, to dismiss the claims entirely you don't need to know the reason for the displayed phenomenon, it is sufficient to know that what is displayed is absurd.

Oh... thank you "poynty point" , I am laughing so hard I can hardly type.


In case you miss the humor, she is telling you that she will answer questions, then she doesn't. She is telling you that she will get her "colleagues to engage", then she doesn't. She is telling you right out front that she doesn't understand or know how to operate a critical item of her equipment, and she is telling you that she actually has no idea how things were set during the trial described by Fig. 3!